EP4CE40F29C8N Altera, EP4CE40F29C8N Datasheet - Page 296

• Manufacturer Part Number: EP4CE40F29C8N
• Description: IC CYCLONE IV FPGA 40K 780FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE40F29C8N

• Number Of Logic Elements/cells: 39600
• Number Of Labs/clbs: 2475
• Total Ram Bits: 1134000
• Number Of I /o: 532
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

1–16
Cyclone IV Device Handbook, Volume 2
1
After updating the word boundary, word aligner status signals (rx_syncstatus
and rx_patterndetect) are driven high for one parallel clock cycle synchronous to
the most significant byte of the word alignment pattern. The rx_syncstatus and
rx_patterndetect signals have the same latency as the datapath and are
forwarded to the FPGA fabric to indicate the word aligner status. Any word
alignment pattern received thereafter in the same word boundary causes only the
rx_patterndetect signal to go high for one clock cycle.
Figure 1–17
width mode. In this example, a /K28.5/ (10'b0101111100) is specified as the word
alignment pattern.
The word aligner aligns to the /K28.5/ alignment pattern (red) in cycle n because the
rx_enapatternalign signal is asserted high. The rx_syncstatus signal goes
high for one clock cycle indicating alignment to a new word boundary. The
rx_patterndetect signal also goes high for one clock cycle to indicate initial word
alignment.
At time n + 1, the rx_enapatternalign signal is deasserted to instruct the word
aligner to lock the current word boundary.
The alignment pattern is detected again (green) in a new word boundary across cycles
n + 2 and n + 3. The word aligner does not align to this new word boundary because
the rx_enapatternalign signal is held low.
The /K28.5/ word alignment pattern is detected again (blue) in the current word
boundary during cycle n + 5 causing the rx_patterndetect signal to go high for
one parallel clock cycle.
Figure 1–17. Word Aligner in 10-bit Manual Alignment Mode
If the word alignment pattern is known to be unique and does not appear between
word boundaries, you can hold the rx_enapatternalign signal constantly high
because there is no possibility of false word alignment. If there is a possibility of the
word alignment pattern occurring across word boundaries, you must control the
rx_enapatternalign signal to lock the word boundary after the desired word
alignment is achieved to avoid re-alignment to an incorrect word boundary.
rx_enapatternalign
rx_patterndetect
rx_dataout[9..0]
shows the manual alignment mode word aligner operation in 10-bit data
rx_syncstatus
rx_clock
MSB
111110000
LSB
n
0101111100 111110000 1111001010 1000000101 111110000 0101111100
n + 1
n + 2
n + 3
Chapter 1: Cyclone IV Transceivers Architecture
n + 4
© December 2010 Altera Corporation
n + 5
MSB
Receiver Channel Datapath
LSB