EP4CE40F29C8N Altera, EP4CE40F29C8N Datasheet - Page 399

• Manufacturer Part Number: EP4CE40F29C8N
• Description: IC CYCLONE IV FPGA 40K 780FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE40F29C8N

• Number Of Logic Elements/cells: 39600
• Number Of Labs/clbs: 2475
• Total Ram Bits: 1134000
• Number Of I /o: 532
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 3: Cyclone IV Dynamic Reconfiguration
Dynamic Reconfiguration Controller Port List
Offset Cancellation Feature
Figure 3–2. ALTGX and ALTGX_RECONFIG Connection for the Offset Cancellation Process
Note to
(1) This block is active during the offset cancellation process.
© December 2010 Altera Corporation
Figure
3–2:
1
1
reconfig_clk
The Cyclone IV GX devices provide an offset cancellation circuit per receiver channel
to counter the offset variations due to process, voltage, and temperature (PVT). These
variations create an offset in the analog circuit voltages, pushing them out of the
expected range. In addition to reconfiguring the transceiver channel, the dynamic
reconfiguration controller performs offset cancellation on all receiver channels
connected to it on power up.
The Offset cancellation for Receiver channels option is automatically enabled in
both the ALTGX and ALTGX_RECONFIG MegaWizard Plug-In Managers for
Receiver and Transmitter and Receiver only configurations. It is not available for
Transmitter only configurations. For Receiver and Transmitter and Receiver only
configurations, you must connect the necessary interface signals between the
ALTGX_RECONFIG and ALTGX (with receiver channels) instances.
Offset cancellation is automatically executed once every time the device is powered
on. The control logic for offset cancellation is integrated into the dynamic
reconfiguration controller. You must connect the ALTGX_RECONFIG instance to the
ALTGX instances (with receiver channels) in your design. You must connect the
reconfig_fromgxb, reconfig_togxb, and necessary clock signals to both the
ALTGX_RECONFIG and ALTGX (with receiver channels) instances.
When the device powers up, the dynamic reconfiguration controller initiates offset
cancellation on the receiver channel by disconnecting the receiver input pins from the
receiver data path. Subsequently, the offset cancellation process goes through
different states and culminates in the offset cancellation of the receiver buffer.
Offset cancellation process only occurs one time after power up and does not occur
when subsequent reconfig_reset is asserted. If you assert reconfig_reset
after the offset cancellation process is completed, the offset cancellation process will
not run again.
If you assert reconfig_reset upon power up; offset cancellation will not begin
until reconfig_reset is deasserted. If you assert reconfig_reset after power
up but before offset cancellation process is completed; offset cancellation will not
complete and restart only when reconfig_reset is deasserted.
Figure 3–2
The dynamic reconfiguration controller sends and receives data to the transceiver
channel through the reconfig_togxb and reconfig_fromgxb signals.
ALTGX_RECONFIG
shows the connection for offset cancellation mode.
offset cancellation
circuit
reconfig_fromgxb[n..0]
reconfig_togxb[3..0]
busy
TX PCS
RX PCS
ALTGX
Cyclone IV Device Handbook, Volume 2
+ CDR (1)
TX PMA
RX PMA
3–9