EP4CE40F29C8N Altera, EP4CE40F29C8N Datasheet - Page 109

• Manufacturer Part Number: EP4CE40F29C8N
• Description: IC CYCLONE IV FPGA 40K 780FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE40F29C8N

• Number Of Logic Elements/cells: 39600
• Number Of Labs/clbs: 2475
• Total Ram Bits: 1134000
• Number Of I /o: 532
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

© December 2010 Altera Corporation
CYIV-51006-2.2
This chapter describes the I/O and high speed I/O capabilities and features offered in
Cyclone
The I/O capabilities of Cyclone IV devices are driven by the diversification of I/O
standards in many low-cost applications, and the significant increase in required I/O
performance. Altera’s objective is to create a device that accommodates your key
board design needs with ease and flexibility.
The I/O flexibility of Cyclone IV devices is increased from the previous generation
low-cost FPGAs by allowing all I/O standards to be selected on all I/O banks.
Improvements to on-chip termination (OCT) support and the addition of true
differential buffers have eliminated the need for external resistors in many
applications, such as display system interfaces.
High-speed differential I/O standards have become popular in high-speed interfaces
because of their significant advantages over single-ended I/O standards. The
Cyclone IV devices support LVDS, BLVDS, RSDS, mini-LVDS, and PPDS. The
transceiver reference clocks and the existing general-purpose I/O (GPIO) clock input
features also support the LVDS I/O standards.
The Quartus
that allow you to plan and optimize I/O system designs even before the design files
are available.
This chapter includes the following sections:
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“Cyclone IV I/O Elements” on page 6–2
“I/O Element Features” on page 6–3
“OCT Support” on page 6–7
“I/O Standards” on page 6–12
“Termination Scheme for I/O Standards” on page 6–13
“I/O Banks” on page 6–16
“Pad Placement and DC Guidelines” on page 6–22
“Clock Pins Functionality” on page 6–23
“High-Speed I/O Interface” on page 6–23
“High-Speed I/O Standards Support” on page 6–27
“True Output Buffer Feature” on page 6–35
“High-Speed I/O Timing” on page 6–36
“Design Guidelines” on page 6–38
“Software Overview” on page 6–39
®
IV devices.
®
II software completes the solution with powerful pin planning features
6. I/O Features in Cyclone IV Devices
Cyclone IV Device Handbook, Volume 1