EP4CE40F29C8N Altera, EP4CE40F29C8N Datasheet - Page 45

• Manufacturer Part Number: EP4CE40F29C8N
• Description: IC CYCLONE IV FPGA 40K 780FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE40F29C8N

• Number Of Logic Elements/cells: 39600
• Number Of Labs/clbs: 2475
• Total Ram Bits: 1134000
• Number Of I /o: 532
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 3: Memory Blocks in Cyclone IV Devices
Memory Modes
Simple Dual-Port Mode
Table 3–3. Cyclone IV Devices M9K Block Mixed-Width Configurations (Simple Dual-Port Mode)
© November 2009 Altera Corporation
8192 × 1
4096 × 2
2048 × 4
1024 × 8
512 × 16
256 × 32
1024 × 9
512 × 18
256 × 36
Read Port
8192
v
v
v
v
v
v
—
—
—
× 1
Simple dual-port mode supports simultaneous read and write operations to different
locations.
Figure 3–8. Cyclone IV Devices Simple Dual-Port Memory
Note to
(1) Simple dual-port RAM supports input or output clock mode in addition to the read or write clock mode shown.
Cyclone IV devices M9K memory blocks support mixed-width configurations,
allowing different read and write port widths.
configurations.
In simple dual-port mode, M9K memory blocks support separate wren and rden
signals. You can save power by keeping the rden signal low (inactive) when not
reading. Read-during-write operations to the same address can either output “Don’t
Care” data at that location or output “Old Data”. To choose the desired behavior, set
the Read-During-Write option to either Don’t Care or Old Data in the RAM
MegaWizard Plug-In Manager in the Quartus II software. For more information about
this behavior, refer to
4096
v
v
v
v
v
v
—
—
—
Figure
× 2
Figure 3–8
3–8:
2048
v
v
v
v
v
v
—
—
—
× 4
shows the simple dual-port memory configuration.
“Read-During-Write Operations” on page
1024
v
v
v
v
v
v
—
—
—
data[ ]
wraddress[ ]
wren
byteena[]
wr_addressstall
wrclock
wrclocken
aclr
× 8
Write Port
512
v
v
v
v
v
v
—
—
—
× 16
256
rd_addressstall
Table 3–3
v
v
v
v
v
v
—
—
—
rdaddress[ ]
× 32
rdclocken
rdclock
(Note 1)
rden
q[ ]
1024
lists mixed-width
Cyclone IV Device Handbook, Volume 1
—
—
—
—
—
—
v
v
v
× 9
3–15.
512
—
—
—
—
—
—
v
v
v
× 18
256
v
v
v
—
—
—
—
—
—
× 36
3–9