PIC18F67K22-I/MR Microchip Technology, PIC18F67K22-I/MR Datasheet - Page 67

• Manufacturer Part Number: PIC18F67K22-I/MR
• Description: 128kB Flash, 4kB RAM, 1kB EE, NanoWatt XLP, GP 64 QFN 9x9x0.9mm TUBE
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F67K22-I/MR

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 64MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

REGISTER 4-3:
 2009-2011 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
PSPMD
R/W-0
RTCCMD can only be set to ‘1’ after an EECON2 unlock sequence. Refer to
Clock and Calendar (RTCC)”
PSPMD: Peripheral Module Disable (PMD) PSP Enable/Disable bit
1 = PMD is enabled for PSP, disabling all of its clock sources
0 = PMD is disabled for PSP
CTMUMD: PMD CTMU Enable/Disable bit
1 = PMD is enabled for CTMU, disabling all of its clock sources
0 = PMD is disabled for CTMU
RTCCMD: PMD RTCC Enable/Disable bit
1 = PMD is enabled for RTCC, disabling all of its clock sources
0 = PMD is disabled for RTCC
TMR4MD: TMR4MD Disable bit
1 = PMD is enabled and all TMR4MD clock sources are disabled
0 = PMD is disabled and TMR4MD is enabled
TMR3MD: TMR3MD Disable bit
1 = PMD is enabled and all TMR3MD clock sources are disabled
0 = PMD is disabled and TMR3MD is enabled
TMR2MD: TMR2MD Disable bit
1 = PMD is enabled and all TMR2MD clock sources are disabled
0 = PMD is disabled and TMR2MD is enabled
TMR1MD: TMR1MD Disable bit
1 = PMD is enabled and all TMR1MD clock sources are disabled
0 = PMD is disabled and TMR1MD is enabled
EMBMD: PMD EMB Enable/Disable bit
1 = PMD is enabled for EMB, disabling all of its clock sources
0 = PMD is disabled for EMB
CTMUMD
R/W-0
PMD1: PERIPHERAL MODULE DISABLE REGISTER 1
W = Writable bit
‘1’ = Bit is set
RTCCMD
R/W-0
(1)
for the unlock sequence
TMR4MD
R/W-0
(1)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
PIC18F87K22 FAMILY
TMR3MD
R/W-0
(Example
TMR2MD
R/W-0
18-1).
Section 18.0 “Real-Time
x = Bit is unknown
TMR1MD
R/W-0
DS39960D-page 67
EMBMD
R/W-0
bit 0