PIC18F67K22-I/MR Microchip Technology, PIC18F67K22-I/MR Datasheet - Page 188

• Manufacturer Part Number: PIC18F67K22-I/MR
• Description: 128kB Flash, 4kB RAM, 1kB EE, NanoWatt XLP, GP 64 QFN 9x9x0.9mm TUBE
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F67K22-I/MR

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 64MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F87K22 FAMILY
TABLE 12-17: PORTJ FUNCTIONS
TABLE 12-18: SUMMARY OF REGISTERS ASSOCIATED WITH PORTJ
DS39960D-page 188
RJ0/ALE
RJ1/OE
RJ2/WRL
RJ3/WRH
RJ4/BA0
RJ5/CE
RJ6/LB
RJ7/UB
Legend:
PORTJ
LATJ
TRISJ
PADCFG1
Legend: Shaded cells are not used by PORTJ.
Note 1:
Pin Name
Name
(1)
(1)
(1)
O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Trigger Buffer Input,
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Unimplemented on 64-pin devices (PIC18F6XK22), read as ‘0’.
Function
TRISJ7
LATJ7
RDPU
Bit 7
WRH
RJ7
WRL
ALE
BA0
RJ0
RJ1
RJ2
RJ3
RJ4
RJ5
RJ6
RJ7
OE
CE
UB
LB
Setting
TRISJ6
LATJ6
REPU
TRIS
Bit 6
RJ6
0
1
x
0
1
x
0
1
x
0
1
x
0
1
x
0
1
x
0
1
x
0
1
x
I/O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
RJPU
TRISJ5
LATJ5
Bit 5
RJ5
Type
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
(1)
I/O
ST
ST
ST
ST
ST
ST
ST
ST
TRISJ4
LATJ<0> data output.
PORTJ<0> data input.
External memory interface address latch enable control output; takes
priority over digital I/O.
LATJ<1> data output.
PORTJ<1> data input.
External memory interface output enable control output; takes priority
over digital I/O.
LATJ<2> data output.
PORTJ<2> data input.
External Memory Bus write low byte control; takes priority over
digital I/O.
LATJ<3> data output.
PORTJ<3> data input.
External memory interface write high-byte control; takes priority over
digital I/O.
LATJ<4> data output.
PORTJ<4> data input.
External Memory Interface Byte Address 0 control output; takes
priority over digital I/O.
LATJ<5> data output.
PORTJ<5> data input.
External memory interface chip enable control output; takes priority
over digital I/O.
LATJ<6> data output.
PORTJ<6> data input.
External memory interface lower byte enable control output; takes
priority over digital I/O.
LATJ<7> data output.
PORTJ<7> data input.
External memory interface upper byte enable control output; takes
priority over digital I/O.
LATJ4
Bit 4
RJ4
—
TRISJ3
LATJ3
Bit 3
RJ3
—
RTSECSEL1 RTSECSEL0
TRISJ2
Description
LATJ2
Bit 2
RJ2
 2009-2011 Microchip Technology Inc.
TRISJ1
LATJ1
Bit 1
RJ1
TRISJ0
LATJ0
Bit 0
RJ0
—