PIC18F67K22-I/MR Microchip Technology, PIC18F67K22-I/MR Datasheet - Page 546

• Manufacturer Part Number: PIC18F67K22-I/MR
• Description: 128kB Flash, 4kB RAM, 1kB EE, NanoWatt XLP, GP 64 QFN 9x9x0.9mm TUBE
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F67K22-I/MR

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 64MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F87K22 FAMILY
Timing Diagrams and Specifications
Top-of-Stack Access ........................................................... 89
TSTFSZ............................................................................. 471
Two-Speed Start-up .................................................. 403, 423
Two-Word Instructions
TXSTAx Register
DS39960D-page 546
Transition for Two-Speed Start-up
Transition for Wake from Idle to Run Mode ................ 63
Transition for Wake from Sleep (HSPLL).................... 62
Transition from RC_RUN Mode to
Transition from SEC_RUN Mode to
Transition to RC_RUN Mode ...................................... 61
Capture/Compare/PWM Requirements .................... 513
CLKO and I/O Requirements ............................ 505, 507
EUSART/AUSART Synchronous Receive
EUSART/AUSART Synchronous Transmission
Example SPI Mode Requirements (Master Mode,
Example SPI Mode Requirements (Master Mode,
Example SPI Mode Requirements (Slave Mode,
Example SPI Slave Mode Requirements
External Clock Requirements ................................... 503
HLVD Characteristics................................................ 511
I
I
Internal RC Accuracy (INTOSC) ............................... 504
MSSP I
MSSP I
PLL Clock.................................................................. 504
Program Memory Fetch Requirements (8-bit)........... 506
Program Memory Write Requirements ..................... 508
Reset, Watchdog Timer, Oscillator Start-up
Timer0 and Timer1 External Clock Requirements .... 512
IESO (CONFIG1H, Internal/External Oscillator
Example Cases........................................................... 93
BRGH Bit .................................................................. 331
2
2
C Bus Data Requirements (Slave Mode) ............... 519
C Bus Start/Stop Bits Requirements
(INTOSC to HSPLL).......................................... 423
PRI_RUN Mode .................................................. 61
PRI_RUN Mode (HSPLL) ................................... 59
Requirements.................................................... 522
Requirements.................................................... 522
CKE = 0) ........................................................... 514
CKE = 1) ........................................................... 515
CKE = 0) ........................................................... 516
(CKE = 1) .......................................................... 517
(Slave Mode)..................................................... 518
Timer, Power-up Timer and Brown-out
Reset Requirements ......................................... 510
Switchover Bit ................................................... 406
2
2
C Bus Data Requirements .......................... 521
C Bus Start/Stop Bits Requirements ........... 520
U
Ultra Low-Power Wake-up
V
Voltage Reference Specifications..................................... 500
W
Watchdog Timer (WDT)............................................ 403, 419
WCOL ....................................................... 315, 316, 317, 320
WCOL Status Flag.................................... 315, 316, 317, 320
WWW Address ................................................................. 547
WWW, On-Line Support ....................................................... 8
X
XORLW............................................................................. 471
XORWF ............................................................................ 472
Exit Delay ................................................................... 71
Overview..................................................................... 70
Associated Registers ................................................ 420
Control Register........................................................ 420
During Oscillator Failure ........................................... 424
Programming Considerations ................................... 419
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