PIC18F67K22-I/MR Microchip Technology, PIC18F67K22-I/MR Datasheet - Page 176

• Manufacturer Part Number: PIC18F67K22-I/MR
• Description: 128kB Flash, 4kB RAM, 1kB EE, NanoWatt XLP, GP 64 QFN 9x9x0.9mm TUBE
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F67K22-I/MR

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 64MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

corresponding Data Direction and Output Latch registers
PIC18F87K22 FAMILY
12.5
PORTD is an 8-bit wide, bidirectional port. The
are TRISD and LATD.
All pins on PORTD are implemented with Schmitt
Trigger input buffers. Each pin is individually
configurable as an input or output.
Each of the PORTD pins has a weak internal pull-up. A
single control bit can turn off all the pull-ups. This is
performed by setting bit, RDPU (PADCFG1<7>). The
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are
disabled on all device Resets.
On 80-pin devices, PORTD is multiplexed with the
system bus as part of the external memory interface.
The I/O port and other functions are only available
when the interface is disabled by setting the EBDIS bit
(MEMCON<7>). When the interface is enabled,
PORTD is the low-order byte of the multiplexed
address/data bus (AD<7:0>). The TRISD bits are also
overridden.
TABLE 12-7:
DS39960D-page 176
RD0/PSP0/
AD0/CTPLS
RD1/PSP1/
AD1/T5CKI/
T7G
RD2/PSP2/AD2
Legend:
Note 1:
Note:
Pin Name
2:
PORTD, TRISD and
LATD Registers
O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Trigger Buffer Input,
I
The Parallel Slave Port (PSP) is available only in Microcontroller mode.
This feature is available only on PIC18F8XK22 devices.
These pins are configured as digital inputs
on any device Reset.
2
C = I
2
PORTD FUNCTIONS
Function
C™/SMBus Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
PSP0
PSP1
PSP2
CTPLS
AD0
AD1
AD2
T5CKI
RD0
RD1
RD2
T7G
(2)
(2)
(2)
(1)
(1)
(1)
Setting
TRIS
0
1
x
x
x
0
1
x
x
x
x
0
1
x
x
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
I
I
I
I
I
Type
DIG
TTL
TTL
DIG
DIG
TTL
TTL
DIG
TTL
TTL
I/O
ST
ST
ST
ST
ST
LATD<0> data output.
PORTD<0> data input.
Parallel Slave Port data.
External Memory Address/Data 0.
CTMU pulse generator output.
LATD<1> data output.
PORTD<1> data input.
Parallel Slave Port data.
External Memory Address/Data 1.
Timer5 clock input.
Timer7 external clock gate input.
LATD<2> data output.
PORTD<2> data input.
Parallel Slave Port data.
External Memory Address/Data 2.
PORTD can also be configured as an 8-bit wide micro-
processor port (Parallel Slave Port) by setting control
bit, PSPMODE (TRISE<4>). In this mode, the input
buffers are TTL. For additional information, see
Section 12.11 “Parallel Slave
The PORTD also has the I
RD4, RD5 and RD6. The pins for SPI are also configu-
rable for open-drain output. Open-drain configuration is
selected by setting bit, SSP2OD (ODCON1<0>).
RD0 has a CTMU functionality. RD1 has the functional-
ity for the Timer5 clock input and Timer7 external clock
gate input.
EXAMPLE 12-4:
CLRF
CLRF
MOVLW
MOVWF
PORTD
LATD
0CFh
TRISD
Description
 2009-2011 Microchip Technology Inc.
; Initialize PORTD by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
; Value used to
; initialize data
; direction
; Set RD<3:0> as inputs
; RD<5:4> as outputs
; RD<7:6> as inputs
INITIALIZING PORTD
2
C and SPI functionality on
Port”.