PIC18F67K22-I/MR Microchip Technology, PIC18F67K22-I/MR Datasheet - Page 166

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PIC18F67K22-I/MR

Manufacturer Part Number
PIC18F67K22-I/MR
Description
128kB Flash, 4kB RAM, 1kB EE, NanoWatt XLP, GP 64 QFN 9x9x0.9mm TUBE
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheet

Specifications of PIC18F67K22-I/MR

Core Processor
PIC
Core Size
8-Bit
Speed
64MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-VFQFN Exposed Pad
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18F67K22-I/MRRSL
Manufacturer:
FSC
Quantity:
250
PIC18F87K22 FAMILY
REGISTER 12-1:
DS39960D-page 166
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4-3
bit 2-1
bit 0
Note 1:
R/W-0
RDPU
2:
To enable the actual RTCC output, the RTCOE (RTCCFG<2>) bit must be set.
Unimplemented on 64-pin devices (PIC18F6XK22), read as ‘0’.
RDPU: PORTD Pull-up Enable bit
1 = PORTD pull-up resistors are enabled by individual port latch values
0 = All PORTD pull-up resistors are disabled
REPU: PORTE Pull-up Enable bit
1 = PORTE pull-up resistors are enabled by individual port latch values
0 = All PORTE pull-up resistors are disabled
RJPU: PORTJ Pull-up Enable bit
1 = PORTJ pull-up resistors are enabled by individual port latch values
0 = All PORTJ pull-up resistors are disabled
Unimplemented: Read as ‘0’
RTSECSEL<1:0>: RTCC Seconds Clock Output Select bits
11 = Reserved; do not use
10 = RTCC source clock is selected for the RTCC pin (the pin can be LF-INTOSC or SOSC, depending
01 = RTCC seconds clock is selected for the RTCC pin
00 = RTCC alarm pulse is selected for the RTCC pin
Unimplemented: Read as ‘0’
R/W-0
REPU
on the RTCOSC (CONFIG3L<1>) bit setting)
PADCFG1: PAD CONFIGURATION REGISTER
W = Writable bit
‘1’ = Bit is set
RJPU
R/W-0
(2)
U-0
(2)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U-0
RTSECSEL1
R/W-0
(1)
 2009-2011 Microchip Technology Inc.
(1)
x = Bit is unknown
RTSECSEL0
R/W-0
(1)
U-0
bit 0

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