PIC18F67K22-I/MR Microchip Technology, PIC18F67K22-I/MR Datasheet - Page 282

• Manufacturer Part Number: PIC18F67K22-I/MR
• Description: 128kB Flash, 4kB RAM, 1kB EE, NanoWatt XLP, GP 64 QFN 9x9x0.9mm TUBE
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F67K22-I/MR

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 64MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F87K22 FAMILY
21.3.1
Each MSSP module has four registers for SPI mode
operation. These are:
• MSSPx Control Register 1 (SSPxCON1)
• MSSPx Status Register (SSPxSTAT)
• Serial Receive/Transmit Buffer Register
• MSSPx Shift Register (SSPxSR) – Not directly
SSPxCON1 and SSPxSTAT are the control and status
registers in SPI mode operation. The SSPxCON1
register is readable and writable. The lower 6 bits of
the SSPxSTAT are read-only. The upper two bits of the
SSPxSTAT are read/write.
REGISTER 21-1:
DS39960D-page 282
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
(SSPxBUF)
accessible
R/W-0
SMP
Polarity of clock state is set by the CKP bit (SSPxCON1<4>).
REGISTERS
SMP: Sample bit
SPI Master mode:
1 = Input data is sampled at the end of data output time
0 = Input data is sampled at the middle of data output time
SPI Slave mode:
SMP must be cleared when SPI is used in Slave mode.
CKE: SPI Clock Select bit
1 = Transmit occurs on the transition from active to Idle clock state
0 = Transmit occurs on the transition from Idle to active clock state
D/A: Data/Address bit
Used in I
P: Stop bit
Used in I
S: Start bit
Used in I
R/W: Read/Write Information bit
Used in I
UA: Update Address bit
Used in I
BF: Buffer Full Status bit (Receive mode only)
1 = Receive is complete, SSPxBUF is full
0 = Receive is not complete, SSPxBUF is empty
CKE
R/W-0
SSPxSTAT: MSSPx STATUS REGISTER (SPI MODE)
(1)
2
2
2
2
2
C™ mode only.
C mode only. This bit is cleared when the MSSPx module is disabled; SSPEN is cleared.
C mode only.
C mode only.
C mode only.
W = Writable bit
‘1’ = Bit is set
R-0
D/A
(1)
R-0
P
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
SSPxSR is the shift register used for shifting data in or
out. SSPxBUF is the buffer register to which data
bytes are written to or read from.
In receive operations, SSPxSR and SSPxBUF
together create a double-buffered receiver. When
SSPxSR receives a complete byte, it is transferred to
SSPxBUF and the SSPxIF interrupt is set.
During
double-buffered. A write to SSPxBUF will write to both
SSPxBUF and SSPxSR.
R-0
S
transmission,
R/W
R-0
 2009-2011 Microchip Technology Inc.
x = Bit is unknown
the
R-0
UA
SSPxBUF
R-0
BF
is
bit 0
not