PIC18F67K22-I/MR Microchip Technology, PIC18F67K22-I/MR Datasheet - Page 246

• Manufacturer Part Number: PIC18F67K22-I/MR
• Description: 128kB Flash, 4kB RAM, 1kB EE, NanoWatt XLP, GP 64 QFN 9x9x0.9mm TUBE
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F67K22-I/MR

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 64MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F87K22 FAMILY
REGISTER 19-1:
REGISTER 19-2:
DS39960D-page 246
bit 3-0
Note 1:
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-6
bit 5
bit 4
bit 3
bit 2
bit 1-0
C7TSEL1
R/W-0
2:
The CCP9 and CCP10 modules are not available on devices with 32 Kbytes of program memory
(PIC18FX5K22).
CCPxM<3:0> = 1011 will only reset the timer and not start AN A/D conversion on CCPx match.
CCPxM<3:0>: CCPx Module Mode Select bits
0000 = Capture/Compare/PWM disabled (resets CCPx module)
0001 = Reserved
0010 = Compare mode, toggle output on match (CCPxIF bit is set)
0011 = Reserved
0100 = Capture mode: every falling edge
0101 = Capture mode: every rising edge
0110 = Capture mode: every 4th rising edge
0111 = Capture mode: every 16th rising edge
1000 = Compare mode: initialize CCPx pin low; on compare match, force CCPx pin high (CCPxIF bit is set)
1001 = Compare mode: initialize CCPx pin high; on compare match, force CCPx pin low (CCPxIF bit is set)
1010 = Compare mode: generate software interrupt on compare match (CCPxIF bit is set, CCPx pin
1011 = Compare mode: Special Event Trigger; reset timer on CCPx match (CCPxIF bit is set)
11xx = PWM mode
C7TSEL<1:0>: CCP7 Timer Selection bits
00 = CCP7 is based off of TMR1/TMR2
01 = CCP7 is based off of TMR5/TMR4
10 = CCP7 is based off of TMR5/TMR6
11 = CCP7 is based off of TMR5/TMR8
Unimplemented: Read as ‘0’
C6TSEL0: CCP6 Timer Selection bit
0 = CCP6 is based off of TMR1/TMR2
1 = CCP6 is based off of TMR5/TMR2
Unimplemented: Read as ‘0’
C5TSEL0: CCP5 Timer Selection bit
0 = CCP5 is based off of TMR1/TMR2
1 = CCP5 is based off of TMR5/TMR4
C4TSEL<1:0>: CCP4 Timer Selection bits
00 = CCP4 is based off of TMR1/TMR2
01 = CCP4 is based off of TMR3/TMR4
10 = CCP4 is based off of TMR3/TMR6
11 = Reserved; do not use
C7TSEL0
R/W-0
CCPxCON: CCPx CONTROL REGISTER (CCP4-CCP10 MODULES)
CCPTMRS1: CCP TIMER SELECT REGISTER 1
reflects I/O state)
W = Writable bit
‘1’ = Bit is set
U-0
—
C6TSEL0
R/W-0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
(2)
U-0
—
C5TSEL0
R/W-0
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x = Bit is unknown
C4TSEL1
R/W-0
(1)
C4TSEL0
R/W-0
bit 0