PIC18F67K22-I/MR Microchip Technology, PIC18F67K22-I/MR Datasheet - Page 412

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PIC18F67K22-I/MR

Manufacturer Part Number
PIC18F67K22-I/MR
Description
128kB Flash, 4kB RAM, 1kB EE, NanoWatt XLP, GP 64 QFN 9x9x0.9mm TUBE
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheet

Specifications of PIC18F67K22-I/MR

Core Processor
PIC
Core Size
8-Bit
Speed
64MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-VFQFN Exposed Pad
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18F67K22-I/MRRSL
Manufacturer:
FSC
Quantity:
250
PIC18F87K22 FAMILY
REGISTER 28-8:
DS39960D-page 412
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
CP7
R/C-1
2:
(1)
This bit is available only on PIC18F67K22 and PIC18F87K22 devices.
For the memory size of the blocks, see
CP7: Code Protection bit
1 = Block 7 is not code-protected
0 = Block 7 is code-protected
CP6: Code Protection bit
1 = Block 6 is not code-protected
0 = Block 6 is code-protected
CP5: Code Protection bit
1 = Block 5 is not code-protected
0 = Block 5 is code-protected
CP4: Code Protection bit
1 = Block 4 is not code-protected
0 = Block 4 is code-protected
CP3: Code Protection bit
1 = Block 3 is not code-protected
0 = Block 3 is code-protected
CP2: Code Protection bit
1 = Block 2 is not code-protected
0 = Block 2 is code-protected
CP1: Code Protection bit
1 = Block 1 is not code-protected
0 = Block 1 is code-protected
CP0: Code Protection bit
1 = Block 0 is not code-protected
0 = Block 0 is code-protected
CP6
R/C-1
CONFIG5L: CONFIGURATION REGISTER 5 LOW (BYTE ADDRESS 300008h)
(1)
C = Clearable bit
W = Writable bit
‘1’ = Bit is set
CP5
R/C-1
(1)
(1)
(1)
(1)
(1)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
CP4
R/C-1
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
Figure
(1)
28-6.
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/C-1
CP3
R/C-1
CP2
 2009-2011 Microchip Technology Inc.
x = Bit is unknown
R/C-1
CP1
R/C-1
CP0
bit 0

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