PIC18F67K22-I/MR Microchip Technology, PIC18F67K22-I/MR Datasheet - Page 420

• Manufacturer Part Number: PIC18F67K22-I/MR
• Description: 128kB Flash, 4kB RAM, 1kB EE, NanoWatt XLP, GP 64 QFN 9x9x0.9mm TUBE
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F67K22-I/MR

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 64MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F87K22 FAMILY
28.2.1
Register 28-16
readable and writable register which contains a control
bit that allows software to override the WDT Enable
Configuration bit, but only if the Configuration bit has
disabled the WDT.
REGISTER 28-16: WDTCON: WATCHDOG TIMER CONTROL REGISTER
TABLE 28-2:
DS39960D-page 420
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
RCON
WDTCON
Legend: — = unimplemented, read as ‘ 0 ’. Shaded cells are not used by the Watchdog Timer.
REGSLP
Name
R/W-0
2:
This bit has no effect if the Configuration bits, WDTEN<1:0>, are enabled.
This bit is available only when ENVREG = 1 and RETEN = 0 .
CONTROL REGISTER
shows the WDTCON register. This is a
REGSLP: Regulator Voltage Sleep Enable bit
1 = Regulator goes into Low-Power mode when device’s Sleep mode is enabled
0 = Regulator stays in normal Operation mode when device’s Sleep mode is activated
Unimplemented : Read as ‘ 0 ’
ULPLVL: Ultra Low-Power Wake-up Output bit
Not valid unless ULPEN = 1 .
1 = Voltage on RA0 pin > ~ 0.5V
0 = Voltage on RA0 pin < ~ 0.5V.
SRETEN: Regulator Voltage Sleep Disable bit
1 = If RETEN (CONFIG1L<0>) = 0 and the regulator is enabled, the device goes into Ultra Low-Power
0 = The regulator is on when the device’s Sleep mode is enabled and the Low-Power mode is
Unimplemented : Read as ‘ 0 ’
ULPEN: Ultra Low-Power Wake-up Module Enable bit
1 = Ultra Low-Power Wake-up module is enabled; ULPLVL bit indicates the comparator output
0 = Ultra Low-Power Wake-up module is disabled
ULPSINK: Ultra Low-Power Wake-up Current Sink Enable bit
Not valid unless ULPEN = 1 .
1 = Ultra Low-Power Wake-up current sink is enabled
0 = Ultra Low-Power Wake-up current sink is disabled
SWDTEN: Software Controlled Watchdog Timer Enable bit
1 = Watchdog Timer is on
0 = Watchdog Timer is off
REGSLP
SUMMARY OF WATCHDOG TIMER REGISTERS
IPEN
Bit 7
mode in Sleep
controlled by REGSLP
U-0
—
SBOREN
W = Writable bit
‘1’ = Bit is set
Bit 6
—
ULPLVL
R-x
ULPLVL
Bit 5
CM
SRETEN
R/W-0
SRETEN
(2)
Bit 4
RI
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
(2)
U-0
—
Bit 3
TO
—
(1)
ULPEN
R/W-0
ULPEN
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Bit 2
PD
x = Bit is unknown
ULPSINK
R/W-0
ULPSINK
Bit 1
POR
SWDTEN
SWDTEN
R/W-0
Bit 0
BOR
bit 0
(1)