PIC18F67K22-I/MR Microchip Technology, PIC18F67K22-I/MR Datasheet - Page 162

• Manufacturer Part Number: PIC18F67K22-I/MR
• Description: 128kB Flash, 4kB RAM, 1kB EE, NanoWatt XLP, GP 64 QFN 9x9x0.9mm TUBE
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F67K22-I/MR

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 64MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F87K22 FAMILY
11.5
The RCON register contains the bits used to determine
the cause of the last Reset, or wake-up from Idle or
Sleep modes. RCON also contains the bit that enables
interrupt priorities (IPEN).
REGISTER 11-22: RCON: RESET CONTROL REGISTER
DS39960D-page 162
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
R/W-0
IPEN
RCON Register
IPEN: Interrupt Priority Enable bit
1 = Enable priority levels on interrupts
0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode)
SBOREN: Software BOR Enable bit
For details of bit operation, see
CM: Configuration Mismatch Flag bit
1 = A Configuration Mismatch Reset has not occurred
0 = A Configuration Mismatch Reset has occurred (must be subsequently set in software)
RI: RESET Instruction Flag bit
For details of bit operation, see
TO: Watchdog Timer Time-out Flag bit
For details of bit operation, see
PD: Power-Down Detection Flag bit
For details of bit operation, see
POR: Power-on Reset Status bit
For details of bit operation, see
BOR: Brown-out Reset Status bit
For details of bit operation, see
SBOREN
R/W-1
W = Writable bit
‘1’ = Bit is set
R/W-1
CM
Register
Register
Register
Register
Register
Register
R/W-1
RI
5-1.
5-1.
5-1.
5-1.
5-1.
5-1.
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R-1
TO
R-1
PD
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x = Bit is unknown
R/W-0
POR
R/W-0
BOR
bit 0