PIC18F67K22-I/MR Microchip Technology, PIC18F67K22-I/MR Datasheet - Page 253

• Manufacturer Part Number: PIC18F67K22-I/MR
• Description: 128kB Flash, 4kB RAM, 1kB EE, NanoWatt XLP, GP 64 QFN 9x9x0.9mm TUBE
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F67K22-I/MR

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 64MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

FIGURE 19-2:
TABLE 19-5:
 2009-2011 Microchip Technology Inc.
INTCON
RCON
PIR4
PIE4
IPR4
TRISB
TRISC
TRISE
TRISH
TMR1L
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by Capture/Compare or Timer1/3/5/7.
Note 1:
Name
2:
(2)
Note:
Unimplemented on devices with a program memory of 32 Kbytes (PIC18F65K22 and PIC18F85K22).
Unimplemented on 64-pin devices (PIC18F6XK22), read as ‘0’.
1
Timer1 Register Low Byte
0
CCP10IF
CCP10IE
CCP10IP
CCPR5H
TMR1H
TMR5H
GIE/GIEH
This block diagram uses CCP4 and CCP5, and their appropriate timers as an example. For details on all of
the CCP modules and their timer assignments, see
REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, TIMER1/3/5/7
TRISB7
TRISC7
TRISE7
TRISH7
IPEN
Bit 7
Comparator
COMPARE MODE OPERATION BLOCK DIAGRAM
CCPR4H
TMR1H
TMR5H
(1)
(1)
(1)
C4TSEL0
C4TSEL1
CCPR5L
TMR1L
Comparator
TMR5L
PEIE/GIEL
CCP9IE
CCP9IP
CCP9IF
SBOREN
TRISB6
TRISC6
TRISE6
TRISH6
Bit 6
CCPR4L
TMR1L
TMR5L
Compare
C5TSEL0
Match
(1)
(1)
(1)
0
1
Set CCP5IF
Compare
TMR0IE
CCP8IF
CCP8IE
CCP8IP
TRISC5
TRISH5
Match
TRISB5
TRISE5
Bit 5
CM
Set CCP4IF
CCP7IE
CCP7IP
CCP7IF
TRISB4
TRISC4
TRISE4
TRISH4
INT0IE
Special Event Trigger
Bit 4
(Timer1/5 Reset)
CCP5CON<3:0>
(Timer1/Timer3 Reset, A/D Trigger)
RI
PIC18F87K22 FAMILY
Output
Table 19-2
Logic
4
Special Event Trigger
CCP4CON<3:0>
CCP6IE
CCP6IP
CCP6IF
TRISB3
TRISC3
TRISE3
TRISH3
Output
Logic
4
RBIE
Bit 3
TO
and
S
R
Table
Q
TMR0IF
CCP5IF
CCP5IE
CCP5IP
TRISC2
TRISH2
TRISB2
TRISE2
19-3.
S
R
Bit 2
Output Enable
PD
Q
TRIS
Output Enable
CCP4IF
CCP4IE
CCP4IP
TRISB1
TRISC1
TRISH1
TRISE1
CCP5 Pin
INT0IF
TRIS
Bit 1
POR
DS39960D-page 253
CCP4 Pin
CCP3IF
CCP3IE
CCP3IP
TRISC0
TRISH0
TRISB0
TRISE0
RBIF
Bit 0
BOR