PIC18F67K22-I/MR Microchip Technology, PIC18F67K22-I/MR Datasheet - Page 118

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PIC18F67K22-I/MR

Manufacturer Part Number
PIC18F67K22-I/MR
Description
128kB Flash, 4kB RAM, 1kB EE, NanoWatt XLP, GP 64 QFN 9x9x0.9mm TUBE
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheet

Specifications of PIC18F67K22-I/MR

Core Processor
PIC
Core Size
8-Bit
Speed
64MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-VFQFN Exposed Pad
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18F67K22-I/MRRSL
Manufacturer:
FSC
Quantity:
250
PIC18F87K22 FAMILY
7.5.1
The sequence of events for programming an internal
program memory location should be:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. Write 0xAA to EECON2.
11. Set the WR bit. This will begin the write cycle.
12. Re-enable the interrupts.
13. Verify the memory (table read).
DS39960D-page 118
Read the 64 or 128 bytes into RAM.
Update the data values in RAM as necessary.
Load the Table Pointer register with the address
being erased.
Execute the row erase procedure.
Load the Table Pointer register with the address
of the first byte being written.
Write the 64 or 128 bytes into the holding
registers with auto-increment.
Set the EECON1 register for the write operation:
• Set the EEPGD bit to point to program memory
• Clear the CFGS bit to access program memory
• Set the WREN to enable byte writes
Disable the interrupts.
Write 0x55 to EECON2.
The CPU will stall for duration of the write for T
(see Parameter D133A).
FLASH PROGRAM MEMORY WRITE
SEQUENCE
IW
An example of the required code is shown in
Example
Note:
Note:
7-3.
Before setting the WR bit, the Table
Pointer address needs to be within the
intended address range of the 64 or
128 bytes in the holding register.
Self-write
EEPROM memory cannot be done while
running in LP Oscillator mode (Low-Power
mode). Therefore, executing a self-write
will put the device into High-Power mode.
 2009-2011 Microchip Technology Inc.
execution
to
Flash
and

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