PIC18F67K22-I/MR Microchip Technology, PIC18F67K22-I/MR Datasheet - Page 218

• Manufacturer Part Number: PIC18F67K22-I/MR
• Description: 128kB Flash, 4kB RAM, 1kB EE, NanoWatt XLP, GP 64 QFN 9x9x0.9mm TUBE
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F67K22-I/MR

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 64MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F87K22 FAMILY
16.5.2
The Timer3/5/7 gate source can be selected from one
of four different sources. Source selection is controlled
by the TxGSS<1:0> bits (TxGCON<1:0>). The polarity
for each available source is also selectable and is
controlled by the TxGPOL bit (TxGCON <6>).
TABLE 16-2:
16.5.2.1
The TxG pin is one source for Timer3/5/7 gate control. It
can be used to supply an external source to the Timerx
gate circuitry.
16.5.2.2
The TMR(x+1) register will increment until it matches the
value in the PR(x+1) register. On the very next increment
cycle, TMR2 will be reset to 00h. When this Reset
occurs, a low-to-high pulse will automatically be gener-
ated and internally supplied to the Timerx gate circuitry.
The pulse will remain high for one instruction cycle and
will return back to a low state until the next match.
Depending on TxGPOL, Timerx increments differently
when
TxGPOL = 1, Timerx increments for a single instruction
FIGURE 16-3:
DS39960D-page 218
TxGSS<1:0>
Timer3/5/7
TMRxGE
TxGPOL
TxGVAL
TxG_IN
TxGTM
00
01
10
11
TxCKI
TMR(x+1)
TIMER3/5/7 GATE SOURCE
SELECTION
TxG Pin Gate Operation
Timer4/6/8 Match Gate Operation
Timerx Gate Pin
TMR(x+1) to Match PR(x+1)
(TMR(x+1) increments to match
PR(x+1))
Comparator 1 Output
(comparator logic high output)
Comparator 2 Output
(comparator logic high output)
TIMER3/5/7 GATE SOURCES
N
TIMER3/5/7 GATE TOGGLE MODE
matches
Timerx Gate Source
PR(x+1).
N + 1 N + 2 N + 3
When
possible to measure the full cycle length of a Timer3/5/7
cycle following a TMR(x+1) match with PR(x+1). When
TxGPOL = 0, Timerx increments continuously, except
for the cycle following the match, when the gate signal
goes from low-to-high.
16.5.2.3
The output of Comparator 1 can be internally supplied
to the Timerx gate circuitry. After setting up
Comparator 1 with the CM1CON register, Timerx will
increment depending on the transitions of the
CMP1OUT (CMSTAT<5>) bit.
16.5.2.4
The output of Comparator 2 can be internally supplied
to the Timerx gate circuitry. After setting up
Comparator 2 with the CM2CON register, Timerx will
increment depending on the transitions of the
CMP2OUT (CMSTAT<6>) bit.
16.5.3
When Timer3/5/7 Gate Toggle mode is enabled, it is
gate signal, as opposed to the duration of a single level
pulse.
The Timerx gate source is routed through a flip-flop that
changes state on every incrementing edge of the
signal. (For timing details, see
The TxGVAL bit will indicate when the Toggled mode is
active and the timer is counting.
Timer3/5/7 Gate Toggle mode is enabled by setting the
TxGTM bit (TxGCON<5>). When the TxGTM bit is
cleared, the flip-flop is cleared and held clear. This is
necessary in order to control which edge is measured.
N + 4
TIMER3/5/7 GATE TOGGLE MODE
Comparator 1 Output Gate
Operation
Comparator 2 Output Gate
Operation
 2009-2011 Microchip Technology Inc.
N + 5 N + 6 N + 7
Figure
16-3.)
N + 8