PIC18F67K22-I/MR Microchip Technology, PIC18F67K22-I/MR Datasheet - Page 278

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PIC18F67K22-I/MR

Manufacturer Part Number
PIC18F67K22-I/MR
Description
128kB Flash, 4kB RAM, 1kB EE, NanoWatt XLP, GP 64 QFN 9x9x0.9mm TUBE
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheet

Specifications of PIC18F67K22-I/MR

Core Processor
PIC
Core Size
8-Bit
Speed
64MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-VFQFN Exposed Pad
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18F67K22-I/MRRSL
Manufacturer:
FSC
Quantity:
250
PIC18F87K22 FAMILY
FIGURE 20-16:
FIGURE 20-17:
FIGURE 20-18:
DS39960D-page 278
Note 1: Port outputs are configured as displayed when
P1<D:A>
PORT Data
PORT Data
PORT Data
PORT Data
STRn
P1<D:A>
PxA Signal
PWM
2: Single PWM output requires setting at least
CCPxM1
CCPxM0
CCPxM1
CCPxM0
STRC
STRD
STRA
STRB
STRn
PWM
the CCPxCON register bits, PxM<1:0> = 00
and CCP1M<3:2> = 11.
one of the STRx bits.
(2)
(2)
(2)
(2)
PORT Data
SIMPLIFIED STEERING
BLOCK DIAGRAM
EXAMPLE OF STEERING EVENT AT END OF INSTRUCTION (STRSYNC = 0)
EXAMPLE OF STEERING EVENT AT BEGINNING OF INSTRUCTION (STRSYNC = 1)
1
0
1
0
1
0
1
0
PORT Data
PWM Period
TRIS
TRIS
TRIS
TRIS
Output Pin
Output Pin
Output Pin
Output Pin
(1)
(1)
(1)
(1)
P1n = PWM
20.4.7.1
The STRSYNC bit of the PSTRxCON register gives the
user two choices for when the steering event will
happen. When the STRSYNC bit is ‘0’, the steering
event will happen at the end of the instruction that
writes to the PSTRxCON register. In this case, the out-
put signal at the Px<D:A> pins may be an incomplete
PWM waveform. This operation is useful when the user
firmware needs to immediately remove a PWM signal
from the pin.
When the STRSYNC bit is ‘1’, the effective steering
update will happen at the beginning of the next PWM
period. In this case, steering on/off the PWM output will
always produce a complete PWM waveform.
Figures
of the PWM steering depending on the STRSYNC
setting.
P1n = PWM
20-17
Steering Synchronization
and
 2009-2011 Microchip Technology Inc.
20-18
PORT Data
illustrate the timing diagrams
PORT Data

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