PIC18F67K22-I/MR Microchip Technology, PIC18F67K22-I/MR Datasheet - Page 187

• Manufacturer Part Number: PIC18F67K22-I/MR
• Description: 128kB Flash, 4kB RAM, 1kB EE, NanoWatt XLP, GP 64 QFN 9x9x0.9mm TUBE
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F67K22-I/MR

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 64MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

TABLE 12-16: SUMMARY OF REGISTERS ASSOCIATED WITH PORTH
12.10 PORTJ, TRISJ and
PORTJ is an 8-bit wide, bidirectional port. The
corresponding Data Direction and Output Latch registers
are TRISJ and LATJ.
All pins on PORTJ are implemented with Schmitt
Trigger input buffers. Each pin is individually
configurable as an input or output.
When the external memory interface is enabled, all of
the PORTJ pins function as control outputs for the inter-
face. This occurs automatically when the interface is
enabled
(MEMCON<7>). The TRISJ bits are also overridden.
 2009-2011 Microchip Technology Inc.
PORTH
LATH
TRISH
ANCON1
ANCON2
ODCON2
Note 1:
Note:
Note:
Name
(1)
2:
(1)
(1)
LATJ Registers
by
PORTJ is available only on 80-pin devices.
Unimplemented on 64-pin devices (PIC18F6XK22), read as ‘0’.
Unimplemented on PIC18FX5K22 devices, read as ‘0’.
These pins are configured as digital inputs
on any device Reset.
CCP10OD
clearing
ANSEL15
ANSEL23
TRISH7
LATH7
Bit 7
RH7
(2)
the
CCP9OD
ANSEL14
ANSEL22
TRISH6
LATH6
Bit 6
RH6
EBDIS
(2)
control
ANSEL13
ANSEL21
CCP8OD
TRISH5
LATH5
Bit 5
RH5
bit
ANSEL12
ANSEL20
CCP7OD
TRISH4
LATH4
Bit 4
RH4
PIC18F87K22 FAMILY
Each of the PORTJ pins has a weak internal pull-up.
The pull-ups are provided to keep the inputs at a known
state for the external memory interface while powering
up. A single control bit can turn off all the pull-ups. This
is performed by clearing bit, RJPU (PADCFG1<5>).
The weak pull-up is automatically turned off when the
port pin is configured as an output. The pull-ups are
disabled on any device Reset.
EXAMPLE 12-9:
CLRF
CLRF
MOVLW
MOVWF
ANSEL19
ANSEL11
CCP6OD
TRISH3
LATH3
Bit 3
RH3
PORTJ
LATJ
0CFh
TRISJ
ANSEL10
ANSEL18
CCP5OD
TRISH2
LATH2
; Initialize PORTJ by
; clearing output latches
; Alternate method
; to clear output latches
; Value used to
; initialize data
; direction
; Set RJ3:RJ0 as inputs
; RJ5:RJ4 as output
; RJ7:RJ6 as inputs
Bit 2
RH2
INITIALIZING PORTJ
ANSEL17
CCP4OD
ANSEL9
TRISH1
LATH1
Bit 1
RH1
DS39960D-page 187
ANSEL16
CCP3OD
ANSEL8
TRISH0
LATH0
Bit 0
RH0