PIC18F67K22-I/MR Microchip Technology, PIC18F67K22-I/MR Datasheet - Page 137

• Manufacturer Part Number: PIC18F67K22-I/MR
• Description: 128kB Flash, 4kB RAM, 1kB EE, NanoWatt XLP, GP 64 QFN 9x9x0.9mm TUBE
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F67K22-I/MR

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 64MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

9.6
Data EEPROM memory has its own code-protect bits in
the Configuration Words. External read and write
operations are disabled if code protection is enabled.
The microcontroller itself can both read and write to the
internal data EEPROM, regardless of the state of the
code-protect Configuration bit. Refer to
“Special Features of the CPU”
information.
9.7
There are conditions when the device may not want to
write to the data EEPROM memory. To protect against
spurious EEPROM writes, various mechanisms have
been implemented. On power-up, the WREN bit is
cleared. In addition, writes to the EEPROM are blocked
during
Parameter
The write initiate sequence, and the WREN bit
together, help prevent an accidental write during
brown-out, power glitch or software malfunction.
EXAMPLE 9-3:
 2009-2011 Microchip Technology Inc.
LOOP
Operation During Code-Protect
Protection Against Spurious Write
the
CLRF
CLRF
BCF
BCF
BCF
BSF
BSF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BTFSC
BRA
INCFSZ EEADR, F
BRA
INCFSZ EEADRH, F
BRA
BCF
BSF
33
in
Power-up
Table
EEADR
EEADRH
EECON1, CFGS
EECON1, EEPGD
INTCON, GIE
EECON1, WREN
EECON1, RD
0x55
EECON2
0xAA
EECON2
EECON1, WR
EECON1, WR
$-2
LOOP
LOOP
EECON1, WREN
INTCON, GIE
DATA EEPROM REFRESH ROUTINE
31-13).
Timer
period
for additional
Section 28.0
; Start at address 0
;
; Set for memory
; Set for Data EEPROM
; Disable interrupts
; Enable writes
; Loop to refresh array
; Read current address
;
; Write 55h
;
; Write 0AAh
; Set WR bit to begin write
; Wait for write to complete
; Increment address
; Not zero, do it again
; Increment the high address
; Not zero, do it again
; Disable writes
; Enable interrupts
(T
PWRT
,
PIC18F87K22 FAMILY
9.8
The data EEPROM is a high-endurance, byte address-
able array that has been optimized for the storage of
frequently
variables or other data that is updated often).
Frequently changing values will typically be updated
more often than Specification D124. If this is the case,
an array refresh must be performed. For this reason,
variables that change infrequently (such as constants,
IDs, calibration, etc.) should be stored in Flash program
memory.
A simple data EEPROM refresh routine is shown in
Example
Note:
Using the Data EEPROM
9-3.
If data EEPROM is only used to store
constants and/or data that changes often,
an array refresh is likely not required. See
Specification D124.
changing
information
DS39960D-page 137
(e.g.,
program