PIC18F67K22-I/MR Microchip Technology, PIC18F67K22-I/MR Datasheet - Page 160
![no-image](/images/manufacturer_photos/0/4/439/microchip_technology_sml.jpg)
PIC18F67K22-I/MR
Manufacturer Part Number
PIC18F67K22-I/MR
Description
128kB Flash, 4kB RAM, 1kB EE, NanoWatt XLP, GP 64 QFN 9x9x0.9mm TUBE
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheet
1.PIC18F65K22-EMR.pdf
(550 pages)
Specifications of PIC18F67K22-I/MR
Core Processor
PIC
Core Size
8-Bit
Speed
64MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-VFQFN Exposed Pad
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F67K22-I/MRRSL
Manufacturer:
FSC
Quantity:
250
- Current page: 160 of 550
- Download datasheet (5Mb)
PIC18F87K22 FAMILY
REGISTER 11-20: IPR5: PERIPHERAL INTERRUPT PRIORITY REGISTER 5
DS39960D-page 160
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
TMR7GIP
R/W-1
Unimplemented on devices with a program memory of 32 Kbytes (PIC18FX5K22).
(1)
TMR7GIP: TMR7 Gate Interrupt Priority bit
1 = High priority
0 = Low priority
TMR12IP: TMR12 to PR12 Match Interrupt Priority bit
1 = High priority
0 = Low priority
TMR10IP: TMR10 to PR10 Match Interrupt Priority bit
1 = High priority
0 = Low priority
TMR8IP: TMR8 to PR8 Match Interrupt Priority bit
1 = High priority
0 = Low priority
TMR7IP: TMR7 Overflow Interrupt Priority bit
1 = High priority
0 = Low priority
TMR6IP: TMR6 to PR6 Match Interrupt Priority bit
1 = High priority
0 = Low priority
TMR5IP: TMR5 Overflow Interrupt Priority bit
1 = High priority
0 = Low priority
TMR4IP: TMR4 to PR4 Match Interrupt Priority bit
1 = High priority
0 = Low priority
TMR12IP
R/W-1
(1)
W = Writable bit
‘1’ = Bit is set
TMR10IP
R/W-1
(1)
TMR8IP
R/W-1
(1)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
TMR7IP
(1)
R/W-1
(1)
(1)
(1)
TMR6IP
R/W-1
2009-2011 Microchip Technology Inc.
x = Bit is unknown
TMR5IP
R/W-1
TMR4IP
R/W-1
bit 0
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