HD6417760BP200QS Renesas Electronics America, HD6417760BP200QS Datasheet - Page 876
HD6417760BP200QS
Manufacturer Part Number
HD6417760BP200QS
Description
IC SUPERH MCU ROMLESS 256BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet
1.D6417760BP200ADV.pdf
(1418 pages)
Specifications of HD6417760BP200QS
Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
69
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
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Mailbox 0 is a receive-only box but Mailboxes 1 to 31 can operate as both receive and transmit
boxes, depending on the MBC bits in the Message Control. The following diagram shows the
structure of a Mailbox in detail.
Rev. 2.00 Feb. 12, 2010 Page 792 of 1330
REJ09B0554-0200
Notes: 1. All bits shadowed in gray are reserved and the write value should always be 0. The read value is not guaranteed.
H'100 + N*32
H'102 + N*32
H'104 + N*32
H'106 + N*32
H'108 + N*32
H'10A + N*32
H'10C + N*32
H'10E + N*32
H'110 + N*32
H'112 + N*32
Address
2. ATX and DART are not supported by mailbox 0, and the MBC setting of mailbox 0 is restricted.
15
0
MSG_DATA_0 (first Rx/Tx byte)
14
NMC ATX
13
MSG_DATA_2
MSG_DATA_4
MSG_DATA_6
12
DART
11
Local acceptance filter mask 0 (LAFM0)
Local acceptance filter mask 1 (LAFM1)
Figure 22.3 Mailbox N Structure
STDID[10:0]
10
MBC[2:0]
Data bus
9
TimeStamp[15:0]
EXTID[15:0]
8
7
0
6
CBE
5
MSG_DATA_1
MSG_DATA_3
MSG_DATA_5
MSG_DATA_7
4
RTR IDE
3
DLC[3:0]
2
[17:16]
1
EXTID
0
8/16 bits
8/16 bits
8/16 bits
8/16 bits
8/16 bits
16 bits
16 bits
16 bits
16 bits
16 bits
Access
Size
Time stamp
Field Name
Control
LAFM
Data
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