HD6417760BP200QS Renesas Electronics America, HD6417760BP200QS Datasheet - Page 587
HD6417760BP200QS
Manufacturer Part Number
HD6417760BP200QS
Description
IC SUPERH MCU ROMLESS 256BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet
1.D6417760BP200ADV.pdf
(1418 pages)
Specifications of HD6417760BP200QS
Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
69
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
- Current page: 587 of 1418
- Download datasheet (9Mb)
The WDT is a single-channel timer used to count the clock stabilization time when exiting standby
mode or a temporary standby state in which the clock frequency is changed. It can be used as a
normal watchdog timer or an interval timer.
13.1
The WDT has the following features.
• Can be used to secure clock stabilization time
• Can be switched between watchdog timer mode and interval timer mode
• Internal reset generation in watchdog timer mode
• Interrupt generation in interval timer mode
• Selection of eight counter input clocks
• Power-on reset or manual reset can be selected.
Figure 13.1 shows a block diagram of the WDT.
Used when exiting standby mode or a temporary standby state in which the clock frequency is
changed.
An internal reset is executed on counter overflow.
An interval timer interrupt is generated on counter overflow.
Any of eight clocks can be selected, scaled from the ×1 clock of frequency divider 1 shown in
figure 12.1 in Section 12, Clock Pulse Generator (CPG).
Features
WTCSR : Watchdog timer control/status register
WTCNT : Watchdog timer counter
Standby
clearing
Internal reset
request
Interrupt
request
Legend:
Section 13 Watchdog Timer (WDT)
Figure 13.1 Block Diagram of WDT
Standby
Interrupt
control
control
control
Reset
WTCSR
Clock selection
Bus interface
Overflow
WDT
WTCNT
Frequency divider
Clock selector
Rev. 2.00 Feb. 12, 2010 Page 503 of 1330
Clock
Standby
mode
Frequency
divider 1 ×1
clock
REJ09B0554-0200
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