HD6417760BP200QS Renesas Electronics America, HD6417760BP200QS Datasheet - Page 406

Manufacturer Part Number

HD6417760BP200QS

IC SUPERH MCU ROMLESS 256BGA

Manufacturer

Renesas Electronics America

SuperH® SH7750r

Core Processor

Connectivity

Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB

DMA, LCD, POR, WDT

Number Of I /o

Program Memory Type

Voltage - Supply (vcc/vdd)

1.4 V ~ 1.6 V

Data Converters

Oscillator Type

Operating Temperature

-40°C ~ 85°C

Package / Case

Lead Free Status / RoHS Status

Contains lead / RoHS non-compliant

Program Memory Size

between the Tr cycle and the Tc cycle. Bits A2W2 to A2W0 and A3W2 to A3W0 in WCR2 can be

used to specify the number of cycles from READ command output cycle Tc1 to the first read data

latch cycle Td1 as 1 to 5 cycles independently for areas 2 and 3. This number of cycles

corresponds to the number of synchronous DRAM CAS latency cycles.

(SA: IO ← memory)

In a synchronous DRAM cycle, the BS signal is asserted for one cycle at the beginning of each

data transfer cycle corresponding to a READ or READA command. When the data is accessed in

the fill operation for a cache miss, the 64-bit boundary data including the missing data are first

read by the initial READ command, and then the 16-byte boundary data including the missing

data are read in wraparound mode. READA commands that are subsequently issued are used to

read the 16 bytes of data, which is the remainder of the 32-byte boundary data.

Rev. 2.00 Feb. 12, 2010 Page 322 of 1330

REJ09B0554-0200

Precharge-sel

Note: For DACKn, an example is shown where CHCRn.AL (acknowledge level) = 0 for the DMAC.

Figure 10.16 Basic Timing for Synchronous DRAM Burst Read