HD6417760BP200QS Renesas Electronics America, HD6417760BP200QS Datasheet - Page 854
HD6417760BP200QS
Manufacturer Part Number
HD6417760BP200QS
Description
IC SUPERH MCU ROMLESS 256BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet
1.D6417760BP200ADV.pdf
(1418 pages)
Specifications of HD6417760BP200QS
Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
69
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
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Bit
8
7 to 0
21.3.20 Root Hub Descriptor B Register (HcRhDescriptorB)
HcRhDescriptorB is the second register of two describing the characteristics of the root hub. Set
the bits of this register on initial setup so as to cater for system implementation.
Initial value:
Initial value:
Rev. 2.00 Feb. 12, 2010 Page 770 of 1330
REJ09B0554-0200
R/W:
R/W:
Bit:
Bit:
R/W
R/W
Bit Name
PSM
NDP
31
15
0
0
R/W
R/W
30
14
0
0
R/W
R/W
29
13
0
0
Initial Value
0
H'02
R/W
R/W
28
12
0
0
R/W
R/W
27
11
0
0
R/W
R/W
26
10
0
0
R/W
R/W
R
R/W
R/W
25
0
9
0
Description
Power Switching Mode
This bit specifies the root hub port power switching
control method. It is implementation specific. This bit
is valid only when the NPS bit is cleared to 0.
0: All ports are powered at the same time.
1: Each port is powered individually. This mode
Number of Downstream Ports
These bits specify the number of downstream ports
supported by the root hub. It is implementation-
specific. The value of these bits is H'2. However,
this LSI supports only 1 port for downstream.
R/W
R/W
allows port power to be controlled by either the
global switch or per-port switching. When
HcRhDescriptorB.PPCM = H'0002, the port
responds only to port power commands
(Set/ClearPortPower). When the port mask is
cleared, then the port is controlled only by the
global power switch (Set/ClearGlobalPower).
24
0
8
0
PPCM
DR
R/W
R/W
23
0
7
0
R/W
R/W
22
0
0
6
R/W
R/W
21
0
5
0
R/W
R/W
20
0
4
0
R/W
R/W
19
0
3
0
R/W
R/W
18
0
2
0
R/W
R/W
17
0
1
0
R/W
R/W
16
0
0
0
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