HD6417760BP200QS Renesas Electronics America, HD6417760BP200QS Datasheet - Page 871

• Manufacturer Part Number: HD6417760BP200QS
• Description: IC SUPERH MCU ROMLESS 256BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BP200QS

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Section 22 Controller Area Network 2 (HCAN2)
22.2.2
Block Function
(1) Micro Processor Interface (MPI)
The MPI allows communication between the CPU and the HCAN2 registers/mailboxes to control
the timer unit, memory interface and data controller, etc. It also contains the wakeup control logic
that detects the CAN bus activities and notifies the MPI and the other parts of HCAN2 so that the
HCAN2 can automatically exit the Sleep mode.
The MPI has four registers CANMCR, CANIRR, CANGSR and CANIMR.
(2) Mailbox
Mailboxes are essentially RAM configured as message buffers. There are 32 Mailboxes, and each
mailbox stores the following information.
• CAN message control (identifier, dlc, rtr, ide, etc)
• CAN message data (for CAN data frames)
• Time Stamp for message receive/transmit
• Local Acceptance Filter Mask for mailboxes configured to receive
• 3-bit width Mailbox Configuration, Disable Automatic Re-Transmission bit, Auto-
Transmission of response to remote frame request and New Message Control bit.
(3) Mailbox Control
The Mailbox control supports the following functions.
For received message, it compares the IDs and generates appropriate RAM address and data to
store messages from the CAN interface into the Mailbox, and set/clear the appropriate registers
accordingly.
To transmit message, it runs the internal arbitration to pick the correct priority message and loads
the message from the Mailbox into the buffer of the CAN Interface, and set/clear appropriate
registers accordingly.
Arbitrate Mailbox accesses between the host CPU and the Mailbox Control.
The Mailbox control has registers CANTXPR, CANTXCR, CANTXACK, CANABACK,
CANRXPR, CANRFPR, and CANMBIMR.
Rev. 2.00 Feb. 12, 2010 Page 787 of 1330
REJ09B0554-0200