HD6417760BP200QS Renesas Electronics America, HD6417760BP200QS Datasheet - Page 183
HD6417760BP200QS
Manufacturer Part Number
HD6417760BP200QS
Description
IC SUPERH MCU ROMLESS 256BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet
1.D6417760BP200ADV.pdf
(1418 pages)
Specifications of HD6417760BP200QS
Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
69
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
- Current page: 183 of 1418
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Section 5 Pipelining
operation, never occurs. For example, when FADD follows FDIV with no dependency between
floating-point registers, FADD is not stalled even if both instructions update the cause field of
FPSCR.
Anti-flow dependency can occur only between a preceding double-precision FADD, FMUL,
FSUB, or FTRV and a following FMOV, FLDI0, FLDI1, FABS, FNEG, or FSTS (see figure 5.3
(g)).
If an executing instruction locks any resource—i.e. a function block that performs a basic
operation—a following instruction that happens to attempt to use the locked resource must be
stalled (figure 5.3 (h)). This kind of stall can be compensated by inserting one or more instructions
independent of the locked resource to separate the interfering instructions. For example, when a
load instruction and an ADD instruction that references the loaded value are consecutive, the 2-
cycle stall of the ADD is eliminated by inserting three instructions without dependency. Software
performance can be improved by such instruction scheduling.
Other penalties arise in the event of exceptions or external data accesses, as follows.
• Instruction TLB miss
• Instruction access to external memory (instruction cache miss, etc.)
• Data access to external memory (operand cache miss, etc.)
• Data access to a memory-mapped control register
During the penalty cycles of an instruction TLB miss or external instruction access, no instruction
is issued, but execution of instructions that have already been issued continues. The penalty for a
data access is a pipeline freeze: that is, the execution of uncompleted instructions is interrupted
until the arrival of the requested data. The number of penalty cycles for instruction and data
accesses is largely dependent on the user's memory subsystems.
Rev. 2.00 Feb. 12, 2010 Page 99 of 1330
REJ09B0554-0200
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