HD6417760BP200QS Renesas Electronics America, HD6417760BP200QS Datasheet - Page 399
HD6417760BP200QS
Manufacturer Part Number
HD6417760BP200QS
Description
IC SUPERH MCU ROMLESS 256BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet
1.D6417760BP200ADV.pdf
(1418 pages)
Specifications of HD6417760BP200QS
Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
69
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
- Current page: 399 of 1418
- Download datasheet (9Mb)
When software wait insertion is specified by WCR2, the external wait input RDY signal is also
sampled. RDY signal sampling is shown in figure 10.11. A single-wait cycle as a software wait is
specified in figure 10.11. Sampling is performed at the transition from the Tw state to the T2 state;
therefore, the RDY signal has no effect if asserted in the T1 cycle or in the first Tw cycle. The
RDY signal is sampled on the rising edge of the clock.
Figure 10.11 SRAM Interface Wait Timing (Wait Cycle Insertion by RDY Signal)
Note:
CKIO
A25–A0
CSn
RD/WR
RD
(read)
D31–D0
(read)
WEn
(write)
D31–D0
(write)
BS
RDY
DACKn
(SA: IO ← memory)
DACKn
(SA: IO → memory)
DACKn
(DA)
For DACKn, an example is shown where the acknowledge level (AL) bit in CHCRn
of the DMAC is cleared to 0.
T1
Tw
Twe
Rev. 2.00 Feb. 12, 2010 Page 315 of 1330
T2
REJ09B0554-0200
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