HD6417760BP200QS Renesas Electronics America, HD6417760BP200QS Datasheet - Page 361
HD6417760BP200QS
Manufacturer Part Number
HD6417760BP200QS
Description
IC SUPERH MCU ROMLESS 256BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet
1.D6417760BP200ADV.pdf
(1418 pages)
Specifications of HD6417760BP200QS
Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
69
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
- Current page: 361 of 1418
- Download datasheet (9Mb)
Bit
15
14
13
12
Bit
Name
A3W2
A3W1
A3W0
⎯
Initial
Value
1
1
1
0
R/W
R/W
R/W
R/W
R
Description
Area 3 Wait Control
These bits specify the number of wait cycles to be
inserted for area 3. An external wait input is available for
SRAM and MPX interfaces and is not available for
synchronous DRAM interface. For the case where an
MPX interface setting is made, see table 10.7.
•
000:
001:
010:
011:
100:
101:
110:
111:
•
000:
001:
010:
011:
100:
101:
110:
111:
Reserved
This bit is always read as 0. The write value should
always be 0.
When SRAM interface is in use:
When synchronous DRAM interface is in use*
Inserted wait cycles
0
1
2
3
6
9
12
15
Synchronous DRAM CAS latency cycles
Setting prohibited
1*
2
3
4*
5*
Setting prohibited
Setting prohibited
2
2
2
Rev. 2.00 Feb. 12, 2010 Page 277 of 1330
RDY pin
Disabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
REJ09B0554-0200
1
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