HD6417760BP200QS Renesas Electronics America, HD6417760BP200QS Datasheet - Page 1168

• Manufacturer Part Number: HD6417760BP200QS
• Description: IC SUPERH MCU ROMLESS 256BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BP200QS

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

30.3.14 LCDC Vertical Sync Signal Register (LDVSYNR)
LDVSYNR specifies the vertical (scan direction and vertical direction) sync signal timing of the
LCD module.
Initial value:
Rev. 2.00 Feb. 12, 2010 Page 1084 of 1330
REJ09B0554-0200
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R/W:
Bit:
Bit Name
VSYNW3
VSYNW2
VSYNW1
VSYNW0
⎯
VSYNP10
VSYNP9
VSYNP8
VSYNP7
VSYNP6
VSYNP5
VSYNP4
VSYNP3
VSYNP2
VSYNP1
VSYNP0
NW3
R/W
VSY
15
0
NW2
VSY
R/W
14
0
NW1
VSY
R/W
13
0
Initial Value
0
0
0
0
0
0
0
1
1
1
0
1
1
1
1
1
NW0
VSY
R/W
12
0
11
R
0
-
NP10
R/W
VSY
10
0
R/W
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
VSY
NP9
9
0
Description
Vertical Sync Signal Width
Sets the width of the vertical sync signals (FLM and
Vsync) (unit: line).
Specify a value of (width of vertical sync signal) −1.
Example: For a vertical sync signal width of 1 line.
Reserved
This bit is always read as 0. The write value should
always be 0.
Vertical Sync Signal Output Position
Sets the output position of the vertical sync signals
(FLM and Vsync) (unit: line).
Specify a value of (position of vertical sync signal
output) −2.
DSTN should be set to an odd number value. It is
handled as (setting value+1)/2.
Example: For a 480-line LCD module and a retrace
period of 0 lines (in other words, VTLN= 479 and
the vertical sync signal is active for the first line):
•
•
R/W
VSY
NP8
8
1
Single display
VSYNP = [(1−1)+VTLN]mod(VTLN+1)
Dual address
VSYNP = [(1−1)×2+VTLN]mod(VTLN+1)
VSY
R/W
NP7
7
1
VSYNW = (1−1) = 0 = H'0
= [(1−1)+479]mod(479+1)
= 479mod480 = 479 =H'1DF
= [(1−1)×2+479]mod(479+1)
= 479mod480 = 479 =H'1DF
R/W
VSY
NP6
1
6
R/W
VSY
NP5
5
0
VSY
NP4
R/W
4
1
VSY
R/W
NP3
3
1
VSY
R/W
NP2
2
1
VSY
NP1
R/W
1
1
R/W
VSY
NP0
0
1