HD6417760BP200QS Renesas Electronics America, HD6417760BP200QS Datasheet - Page 240

• Manufacturer Part Number: HD6417760BP200QS
• Description: IC SUPERH MCU ROMLESS 256BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BP200QS

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

7.2.1
CCR selects the cache operating mode, whether all cache entries are disabled, and the cache write
mode.
CCR can be accessed in longwords from H'FF00 001C in the P4 area and from H'1F00 001C in
area 7. CCR modifications must only be made by a program in the non-cached P2 area. After CCR
is updated, an instruction that performs data access to the P0, P1, P3, or U0 area should be located
at least four instructions after the CCR update instruction. Also, a branch instruction to the P0, P1,
P3, or U0 area should be located at least eight instructions after the CCR update instruction.
Initial value:
Initial value:
Rev. 2.00 Feb. 12, 2010 Page 156 of 1330
REJ09B0554-0200
Bit
31
30 to 16 ⎯
15
14 to 12 ⎯
11
R/W:
R/W:
Bit:
Bit:
EMODE
Cache Control Register (CCR)
Bit Name
EMODE
IIX
ICI
R/W
R/W
31
15
IIX
0
0
30
14
R
R
0
0
-
-
29
13
R
R
0
0
-
-
Initial Value
0
All 0
0
All 0
0
28
12
R
R
0
0
-
-
R/W
ICI
27
11
R
0
0
-
26
10
R
R
0
0
-
-
R/W
R/W
R
R/W
R
R/W
25
R
R
0
9
0
-
-
Description
Double-Size Cache Mode Bit
This bit selects whether double-size cache mode
is used or not. Do not write to this bit while cache
is being used.
0: Cache direct mapping mode
1: Double-size cache mode
Reserved
These bits are always read as 0. The write value
should always be 0.
IC Index Enable Bit
0: Effective address bits [12:5] used for IC entry
1: Effective address bits [25] and [11:5] used for
Reserved
These bits are always read as 0. The write value
should always be 0.
IC Invalidation Bit
When 1 is written to this bit, the V bits of all IC
entries are cleared to 0. This bit is always read
as 0.
R/W
ICE
24
R
0
8
0
-
selection
IC entry selection
R/W
OIX
23
R
0
7
0
-
22
R
R
0
0
6
-
-
ORA
R/W
21
R
0
5
0
-
20
R
R
0
4
0
-
-
R/W
OCI
19
R
-
0
3
0
R/W
CB
18
R
0
2
0
-
R/W
WT
17
R
-
0
1
0
OCE
R/W
16
R
0
0
0
-