HD6417760BP200QS Renesas Electronics America, HD6417760BP200QS Datasheet - Page 263
HD6417760BP200QS
Manufacturer Part Number
HD6417760BP200QS
Description
IC SUPERH MCU ROMLESS 256BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet
1.D6417760BP200ADV.pdf
(1418 pages)
Specifications of HD6417760BP200QS
Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
69
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
- Current page: 263 of 1418
- Download datasheet (9Mb)
7.7.2
A write to the SQs can be performed using a store instruction for addresses H'E000 0000 to
H'E3FF FFFC in the P4 area. A longword or quadword access size can be used. The meanings of
the address bits are as follows:
7.7.3
Transfer from the SQs to external memory can be performed with a prefetch instruction (PREF).
Issuing a PREF instruction for addresses H'E000 0000 to H'E3FF FFFC in the P4 area starts a
transfer from the SQs to external memory. The transfer length is fixed at 32 bytes, and the start
address is always at a 32-byte boundary. While the contents of one SQ are being transferred to
external memory, the other SQ can be written to without a penalty cycle. However, writing to the
SQ involved in the transfer to external memory is kept waiting until the transfer is completed.
The external address bits [28:0] of the SQ transfer destination are specified as shown below,
according to whether the MMU is on or off.
• When MMU is on (AT = 1 in MMUCR)
[31:26]
[25:6]
[5]
[4:2]
[1:0]
The SQ area (H'E000 0000 to H'E3FF FFFF) is set in VPN of the UTLB, and the transfer
destination external address in PPN. The ASID, V, SZ, SH, PR, and D bits have the same
meaning as for normal address translation, but the C and WT bits have no meaning with regard
to this page. Transfer to the PCMCIA interface area by means of the SQs is not allowed. When
a prefetch instruction is issued for the SQ area, address translation is performed and external
address bits [28:10] are generated in accordance with the SZ bit specification. For external
address bits [9:5], the address prior to address translation is generated in the same way as when
the MMU is off. External address bits [4:0] are fixed at 0. Transfer from the SQs to external
memory is performed to this address.
Writing to SQ
Transfer to External Memory
: 111000
: Don't care
: 0/1
: LW specification
: 00
Store queue specification
Used for external memory transfer/access right
0: SQ0 specification
1: SQ1 specification
Fixed at 0
Specifies longword position in SQ0/SQ1
Rev. 2.00 Feb. 12, 2010 Page 179 of 1330
REJ09B0554-0200
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