HD6417760BP200QS Renesas Electronics America, HD6417760BP200QS Datasheet - Page 988
HD6417760BP200QS
Manufacturer Part Number
HD6417760BP200QS
Description
IC SUPERH MCU ROMLESS 256BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet
1.D6417760BP200ADV.pdf
(1418 pages)
Specifications of HD6417760BP200QS
Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
69
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
- Current page: 988 of 1418
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24.2.35 Peripheral Module Select Register (IPSELR)
IPSELR is a 16-bit readable/writable register. Modules using pins multiplexed are specified by
this register when the modules are not dependent on either MFI mode or LCD mode. For details of
pin multiplexing, see table 24.1.
This register is valid only when peripheral modules are selected by PACR, PBCR (PTB7 to
PTB5), PDCR, PFCR, or PJCR (PJT5 to PJT3) of the GPIO.
Initial value:
Rev. 2.00 Feb. 12, 2010 Page 904 of 1330
REJ09B0554-0200
Bit
15
14
13
12
R/W:
Bit:
Bit Name
IPSELR15
IPSELR14
IPSELR13
IPSELR12
IPSELR
R/W
15
15
0
IPSELR
R/W
14
14
0
IPSELR
R/W
13
13
0
Initial Value
0
0
0
0
IPSELR
R/W
12
12
0
IPSELR
R/W
11
11
0
IPSELR
R/W
10
R/W
R/W
R/W
R/W
R/W
10
0
IPSELR
R/W
9
9
0
Description
Out of the modules HSPI, MMCIF, and SIM, select
the one using the pins HSPI_TX/SIM_D/MCDAT,
HSPI_RX, HSPI_CLK/SIM_CLK/MCCLK, and
HSPI_CS/SIM_RST/MCCMD.
00: Selects HSPI
01: Selects MMCIF
10: Setting prohibited
11: Selects SIM
using the pins CAN0_NERR/AUDCK,
CAN0_RX/AUDATA[2], CAN0_TX/AUDATA[0],
CAN1_NERR/AUDSYNC, CAN1_RX/AUDATA[3],
and CAN1_TX/AUDATA[1].
0: Selects HCAN2
1: Selects AUD
using the pins Reserved/AUDATA[3],
Reserved/AUDATA[2], Reserved/AUDATA[1],
Reserved/AUDCK, Reserved/AUDSYNC, and
ADTRG/AUDATA[0].
0: Reserved/ADC*
1: AUD
Note: *Pull up the reserved pins internally in the
PKCR register settings.
Out of the modules HCAN2 and AUD, select the one
Out of the modules ADC and AUD, select the one
R
8
-
0
7
0
-
R
R
6
-
0
R
5
0
-
R
4
0
-
R
3
0
-
2
0
R
-
LCDMD
R/W
1
1
1
LCDMD
R/W
0
1
0
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