HD6417760BP200QS Renesas Electronics America, HD6417760BP200QS Datasheet - Page 400

• Manufacturer Part Number: HD6417760BP200QS
• Description: IC SUPERH MCU ROMLESS 256BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BP200QS

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

(3) Read-Strobe Negate Timing
When the SRAM interface is in use, timing for the negation of the strobe during read operations
can be specified by the A1RDH and A4RDH bits in WCR3. When the byte control SRAM
interface is in use, AnRDH should be cleared to 0.
Rev. 2.00 Feb. 12, 2010 Page 316 of 1330
REJ09B0554-0200
Figure 10.12 SRAM Interface Wait State Timing (Read Strobe Negate Timing Setting;
CKIO
A25–A0
CSn
RD/WR
RD
D31–D0
BS
Note: * Where the AnRDH bit is set to 1.
TS1: Setup wait
AnS in WCR3
(0 to 1)
TS1
AnS = 1, AnW = 011, AnH = 10)
T1
Tw
Tw: Access wait
AnW in WCR2
Tw
(0 to 15)
Tw
T2
TH1, TH2: Hold wait
TH1
*
AnH in WCR3
(0 to 3)
TH2