HD6417760BP200QS Renesas Electronics America, HD6417760BP200QS Datasheet - Page 168
HD6417760BP200QS
Manufacturer Part Number
HD6417760BP200QS
Description
IC SUPERH MCU ROMLESS 256BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet
1.D6417760BP200ADV.pdf
(1418 pages)
Specifications of HD6417760BP200QS
Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
69
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
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Table 4.12 Floating-Point Graphics Acceleration Instructions
Instruction
FMOV
FMOV
FMOV
FMOV
FMOV
FMOV
FMOV
FMOV
FMOV
FIPR
FTRV
FRCHG
FSCHG
4.4
4.4.1
• Incorrect data may be written to the cache when a TRAPA instruction or undefined instruction
• The ITLB hit judgment may be incorrect when a TRAPA instruction or undefined instruction
• Incorrect data may be written to an FPU-related register or to the MACH or MACL register
Conditions under which Problem Occurs
1. Incorrect data may be written to the instruction cache when the following three conditions
Rev. 2.00 Feb. 12, 2010 Page 84 of 1330
REJ09B0554-0200
code H'FFFD is executed.
code H'FFFD is executed, causing a multi-hit exception to occur after re-registration.
when a TRAPA instruction, SLEEP instruction, or undefined instruction code H'FFFD is
executed.
occur at the same time.
a. The instruction cache is enabled (CCR.ICE = 1).
b. A TRAPA instruction or undefined instruction code H'FFFD in a cache-enabled area is
executed.
DRm,XDn
XDm,DRn
XDm,XDn
@Rm,XDn
@Rm+,XDn
@(R0,Rm),XDn
XDm,@Rn
XDm,@-Rn
XDm,@(R0,Rn)
FVm,FVn
XMTRX,FVn
Usage Note
Notes on TRAPA Instruction, SLEEP Instruction, and Undefined Instruction
(H'FFFD)
DRm → XDn
Rn – 8 → Rn, XDm → (Rn)
inner_product [FVm, FVn] →
Operation
XDm → DRn
XDm → XDn
(Rm) → XDn
(Rm) → XDn, Rm + 8 → Rm
(R0 + Rm) → XDn
XDm → (Rn)
XDm → (R0 + Rn)
FR[n+3]
transform_vector [XMTRX, FVn]
→ FVn
~FPSCR.FR → FPSCR.FR
~FPSCR.SZ → FPSCR.SZ
Instruction Code
1111nnn1mmm01100 —
1111nnn0mmm11100 —
1111nnn1mmm11100 —
1111nnn1mmmm1000 —
1111nnn1mmmm1001 —
1111nnn1mmmm0110 —
1111nnnnmmm11010 —
1111nnnnmmm11011 —
1111nnnnmmm10111 —
1111nnmm11101101 —
1111nn0111111101 —
1111101111111101 —
1111001111111101 —
Privileged
T Bit
—
—
—
—
—
—
—
—
—
—
—
—
—
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