HD6417760BP200QS Renesas Electronics America, HD6417760BP200QS Datasheet - Page 350
HD6417760BP200QS
Manufacturer Part Number
HD6417760BP200QS
Description
IC SUPERH MCU ROMLESS 256BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet
1.D6417760BP200ADV.pdf
(1418 pages)
Specifications of HD6417760BP200QS
Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
69
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
- Current page: 350 of 1418
- Download datasheet (9Mb)
Rev. 2.00 Feb. 12, 2010 Page 266 of 1330
REJ09B0554-0200
Bit
4
3
2
1
0
Bit
Name
DRAMTP2
DRAMTP1
DRAMTP0
⎯
A56PCM 0
Initial
Value
0
0
0
0
R/W
R/W
R/W
R/W
R
R/W
Description
Areas 2 and 3 Memory Type
These bits specify the type of memory connected to
areas 2 and 3. Memory types such as ROM, SRAM, and
flash ROM can be connected as an SRAM interface.
Synchronous DRAM can also be connected.
000: Areas 2 and 3 are accessed as an SRAM interface
001: Setting prohibited
010: Area 2 is accessed as an SRAM interface or MPX
011: Areas 2 and 3 are accessed as a synchronous
100: Setting prohibited
101: Setting prohibited
110: Setting prohibited
111: Setting prohibited
Note: * The MEMMPX bit setting selects the SRAM
Reserved
This bit is always read as 0. The write value should
always be 0.
Area 5 and 6 Bus Type
Specifies whether areas 5 and 6 are accessed as
PCMCIA interface. The setting of this bit has priority over
the MEMMPX bit. When this bit is 1, the MD3 pin is
designated for output as the CE2A pin, and the MD4 pin
is designated for output as the CE2B pin.
0: Areas 5 and 6 are accessed as SRAM interface
1: Areas 5 and 6 are accessed as PCMCIA interface
or MPX interface
interface
interface
DRAM interface
interface or MPX interface.
*
and area 3 as a synchronous DRAM
*
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