HD6417760BP200QS Renesas Electronics America, HD6417760BP200QS Datasheet - Page 948
HD6417760BP200QS
Manufacturer Part Number
HD6417760BP200QS
Description
IC SUPERH MCU ROMLESS 256BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet
1.D6417760BP200ADV.pdf
(1418 pages)
Specifications of HD6417760BP200QS
Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
69
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
- Current page: 948 of 1418
- Download datasheet (9Mb)
23.4.5
If any of the FBS, CLKP, IDIV or CLKC bit values are changed, then the HSPI software reset is
generated. The receive and transmit FIFO pointers can be initialized by the HSPI software reset.
The data transmission after the HSPI software reset should protect transmitting and receiving
protocol of HSPI, and please perform it from the first. A guarantee of operation is not offered
other than it.
23.4.6
SPCR also allows the user to define the shift timing for transmit data and polarity. The FBS bit in
SPCR allows selection between two different transfer formats. The MSB or LSB is valid on the
falling edge of HSPI_CS. The CLKP bit in SPCR allows for control of the polarity select block
which controls which edges of HSPI_CLK shift and sample data in the master and slave.
23.4.7
The master and slave can be considered linked together as a circular shift register synchronized
with HSPI_CLK. The transmit byte from the master is replaced with the receive byte from the
slave in eight HSPI_CLK cycles. Both the transmit and receive functions are double buffered to
allow for continuous reads and writes. When FIFO mode is enabled eight entry FIFOs are
available for both transmit and receive data.
Rev. 2.00 Feb. 12, 2010 Page 864 of 1330
REJ09B0554-0200
HSPI Software Reset
Clock Polarity and Transmit Control
Transmit and Receive Routines
HSPI_CLK (CLKP = 0)
HSPI_CLK (CLKP = 1)
Data transfer cycle
HSPI_RX
HSPI_CS
HSPI_TX
Figure 23.4 Timing Conditions when FBS = 1
*
MSB
MSB
1
2
6
6
3
5
5
4
4
4
5
3
3
6
2
2
7
1
1
LSB
8
LSB
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