HD6417760BP200QS Renesas Electronics America, HD6417760BP200QS Datasheet - Page 502
HD6417760BP200QS
Manufacturer Part Number
HD6417760BP200QS
Description
IC SUPERH MCU ROMLESS 256BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet
1.D6417760BP200ADV.pdf
(1418 pages)
Specifications of HD6417760BP200QS
Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
69
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
- Current page: 502 of 1418
- Download datasheet (9Mb)
Bit
2
1
0
Rev. 2.00 Feb. 12, 2010 Page 418 of 1330
REJ09B0554-0200
Bit Name
TAR
TDS
TDE
Initial Value
0
0
0
R/W
R/W
R/W
R/W
Description
HAC/SSI Transmit DMA Auto Reload Setting
Specifies the use or unuse of auto address reload
to continue a DMA transfer when the number of
bytes in the transmit DMA transfer reaches the
number of transfer bytes specified by
DMAARXTCRn.
0: Address of transmit DMA not auto reloaded
1: Address of transmit DMA auto reloaded
HAC/SSI Transmit DMA Termination
Setting this bit to 1 forcibly terminates a transmit
DMA transfer.
•
0: Write operation is ignored
1: Transmit DMA transfer is forcibly terminated
•
0: Transfer is completed
1: Transfer is being performed
HAC/SSI Transmit DMA Transfer Activation
Control
Controls the transmit DMA transfer activation.
Write operation is ignored during transfer. To
reactivate a transmit DMA transfer, read this bit as
0 and then write 1 to it.
•
0: Write operation is ignored
1: Transmit DMA transfer is activated
•
0: Transfer is completed
1: Transfer is being performed
When writing
When reading
When writing
When reading
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