HD6417760BP200QS Renesas Electronics America, HD6417760BP200QS Datasheet - Page 850
HD6417760BP200QS
Manufacturer Part Number
HD6417760BP200QS
Description
IC SUPERH MCU ROMLESS 256BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet
1.D6417760BP200ADV.pdf
(1418 pages)
Specifications of HD6417760BP200QS
Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
69
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
- Current page: 850 of 1418
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21.3.16 Frame Number Register (HcFmNumber)
HcFmNumber contains a 16-bit counter. This register is referenced for the timing between events
occurring in HC and HCD. HCD uses 16-bit value specified in this register and generates a 32-bit
frame number without requiring frequent access to the register.
HcFmNumber is a read-only register. Operation is not guaranteed when writing.
Initial value:
Initial value:
Bit
31 to 16
15 to 0
21.3.17 Periodic Start Register (HcPeriodicStart)
HcPeriodicStart indicates the earliest time when HC should start to process the periodic list.
Initial value:
Initial value:
Rev. 2.00 Feb. 12, 2010 Page 766 of 1330
REJ09B0554-0200
R/W:
R/W:
R/W:
R/W:
Bit:
Bit:
Bit:
Bit:
Bit Name
⎯
FN
31
15
31
15
R
R
R
R
0
0
0
0
-
-
-
30
14
30
14
-
R
R
-
R
-
R
0
0
0
0
R/W
29
13
29
13
R
R
R
0
0
0
0
-
-
Initial Value
All 0
All 0
R/W
28
12
28
12
R
R
R
0
0
0
0
-
-
R/W
27
11
27
11
R
R
R
0
0
0
0
-
-
R/W
R/W
R
R
26
10
26
10
R
R
R
-
0
0
-
0
0
R/W
25
25
R
R
R
-
0
9
0
-
0
9
0
Description
Reserved
These bits are always read as 0.
Frame Number
This is incremented when HcFmRemaining is re-
loaded. It will be rolled over to H'0 after H'FFFF.
When HC enters the USB operational state, this will
be automatically incremented. HC increments the FN
at each frame boundary and sends a SOF. Then HC
writes the FN contents to HCCA before reading the
first ED in that Frame. After writing to HCCA, the HC
sets HcInterruptStatus.SF = 1.
R/W
24
24
R
R
R
0
8
0
0
8
0
-
-
R/W
23
23
R
R
R
0
7
0
0
7
0
-
-
FN
PS
R/W
22
22
R
R
R
0
0
0
6
0
6
-
-
R/W
21
21
R
R
R
0
5
0
0
5
0
-
-
R/W
20
20
R
R
R
0
4
0
0
4
0
-
-
R/W
19
19
R
R
R
0
3
0
0
3
0
-
-
R/W
18
18
R
R
R
0
2
0
0
2
0
-
-
R/W
17
17
R
R
R
0
1
0
0
1
0
-
-
R/W
16
16
R
R
R
0
0
0
0
0
0
-
-
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