HD6417760BP200QS Renesas Electronics America, HD6417760BP200QS Datasheet - Page 522
HD6417760BP200QS
Manufacturer Part Number
HD6417760BP200QS
Description
IC SUPERH MCU ROMLESS 256BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet
1.D6417760BP200ADV.pdf
(1418 pages)
Specifications of HD6417760BP200QS
Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
69
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
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• External Request 2-Channel Mode
Table 11.9 (1)
Legend:
O: DACK output setting in dual address mode transfer
Notes: 1. SRAM-type in the table indicates an SRAM, byte control SRAM, or burst ROM.
• DMABRG Mode
Rev. 2.00 Feb. 12, 2010 Page 438 of 1330
REJ09B0554-0200
Table 11.9 (1) shows the memory interfaces that can be specified for the transfer source and
transfer destination in DMA transfer initiated by an external request in external request 2-
channel mode supported by this LSI.
Synchronous DRAM
External device with DACK
SRAM-type
External device with DACK
Synchronous DRAM
SRAM-type, MPX, PCMCIA
SRAM-type, PCMCIA, MPX
SRAM-type, MPX, PCMCIA
Table 11.9 (2) shows the memory interfaces that can be specified for the transfer source and
transfer destination in DMA transfer initiated by an external request in DMABRG mode
supported by this LSI.
Transfer Source
2. Memory interfaces in which transfer is possible in single address mode are SRAM, byte
3. When performing dual address mode transfer, make the DACK output setting for the
control SRAM, burst ROM, and synchronous DRAM.
SRAM, byte control SRAM, burst ROM, PCMCIA, or MPX interface.
Transfer Direction (Settable Memory Interface)
External Request Transfer Sources and Destinations in External Request 2-
Channel Mode
O Synchronous DRAM
O SRAM-type, PCMCIA, MPX
External device with DACK
Synchronous DRAM
External device with DACK
SRAM-type
SRAM-type, MPX, PCMCIA
SRAM-type, MPX, PCMCIA
Transfer Destination
O Dual
O Dual
Single
Single
Single
Single
Dual
Dual
Address
Mode
0, 1
0, 1
0, 1
0, 1
0, 1
0, 1
0, 1
0, 1
Usable
DMAC
Channels
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