HD6417760BP200QS Renesas Electronics America, HD6417760BP200QS Datasheet - Page 1029
HD6417760BP200QS
Manufacturer Part Number
HD6417760BP200QS
Description
IC SUPERH MCU ROMLESS 256BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet
1.D6417760BP200ADV.pdf
(1418 pages)
Specifications of HD6417760BP200QS
Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
69
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
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26.3.4
TBCR is an 8-bit readable/writable register that specifies the number of bytes to be transferred
(block size) for each single block transfer command. TBCR specifies the number of data block
bytes not including the start bit, end bit, and CRC.
The multiblock transfer command corresponds to the number of bytes of each data block. This
setting is ignored by the stream transfer command.
Bit
7 to
4
3
2
1
0
Bit
Name
—
CS3
CS2
CS1
CS0
Transfer Byte Number Count Register (TBCR)
Initial
Value
All 0
0
0
0
0
Initial value:
R/W:
Bit:
R/W
R
R/W
R/W
R/W
R/W
7
-
0
R
Description
These bits are always read as 0. The write value should
always be 0.
Transfer Data Block Size
Four or more bytes should be set before executing a
command with data transfer.
0000: 1 byte (for forced erase)
0001: Setting prohibited
0010: 4 bytes
0011: 8 bytes
0100: 16 bytes
0101: 32 bytes
0110: 64 bytes
0111: 128 bytes
1000: 256 bytes
1001: 512 bytes
1010: 1024 bytes
1011: 2048 bytes
1100 to 1111: Setting prohibited
Reserved
R
6
0
-
R
5
0
-
4
0
R
-
R/W
C3
3
0
Rev. 2.00 Feb. 12, 2010 Page 945 of 1330
R/W
C2
2
0
R/W
C1
1
0
R/W
C0
0
0
REJ09B0554-0200
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