HD64F7047F50 Renesas Electronics America, HD64F7047F50 Datasheet - Page 578

• Manufacturer Part Number: HD64F7047F50
• Description: IC SUPERH MCU FLASH 256K 100QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047F50

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

17.2
1. In this LSI series, individual functions are available as multiplexed functions on multiple pins.
2. To select a pin function, set the port control registers (PACRL3, PACRL2, PACRL1, PBCR1,
3. When external spaces are used, set the data input/output pins as follows by the pin function
4. Regarding the pin in which input/output port is multiplexed with DREQ or IRQ, when the port
5. In a state where the pin is in general I/O mode and set to 1-output (specifically, the port control
Rev. 2.00, 09/04, page 536 of 720
This approach is intended to increase the number of selectable pin functions and to allow the
easier design of boards.
When the pin function controller (PFC) is used to select a function, only a single pin can be
specified for each function. If one function is specified for two or more pins, the function will
not work properly.
PBCR2, PDCRL1, and PDCRL2) before setting the port I/O registers (PAIORL, PBIOR, and
PDIOR). To select the function of the pin which is multiplexed with the port E, the order of
setting the port control registers (PECRH, PECRL1, and PECRL2) and port I/O registers
(PEIORH and PEIORL) is not matter.
controller (PFC), according to the bus size of the CS0 space specified by the bus control
register 1 (BCR1) of the bus state controller.
When the CS space takes the byte (8 bits) size, set all pins D7 to D0 as data input/output pins.
input is changed from low level to DREQ edge or IRQ edge detection mode, the corresponding
edge is detected.
register is in general I/O mode and both the port I/O register and the port data register are set to
1), a power-on reset through the RES pin may generate a low level on this pin upon the power-
on state is realized. To prevent this low level from happening, set the port I/O register to 0
(general output) and then apply the power-on reset. Note, however, that no low level may be
generated internally by the power-on reset due to the WDT overflow.
Precautions for Use