HD64F7047F50 Renesas Electronics America, HD64F7047F50 Datasheet - Page 451

• Manufacturer Part Number: HD64F7047F50
• Description: IC SUPERH MCU FLASH 256K 100QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047F50

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

• CAN message data (for CAN data frames)
• Timestamp for receiving/transmitting messages
• Sets the local acceptance filter mask (LAFM) for reception or the trigger time for transmission.
• Configures a 3 bit-wide mailbox, disables the automatic retransmission bit, and transmits the
Mailbox Control: The mailbox control handles the following functions.
For received messages, compares the IDs, generates appropriate RAM addresses/data to store
messages from the mailbox in the CAN interface, and sets or clears the corresponding registers.
To transmit messages, executes the internal arbitration, regardless of whether an event trigger or a
time trigger, to select the correct priority message, loads the message from the mailbox into the
CAN interface transmit buffer, and sets or clears the corresponding registers each time.
Arbitrates accesses between the host CPU and mailbox.
Includes registers such as TXPR, TXCR, TXACK, ABACK, RXPR, RFPR, MBIMR, and UMSR.
Timer: The timer is used as a supporting function for transmitting and receiving the messages that
record HCAN2-specific time frames and results. The timer is a 16-bit free-running up counter
controllable by the host CPU. Two compare match registers generate the interrupt signal to clear
the counter values and set the local offset registers. They also cancel the transmit wait messages.
Two input capture registers record the timestamps on the CAN message and globally synchronize
the timer values in the CAN system. A comparison match function of CAN-ID on each mailbox
allows transmission to be cancelled. The timer clock cycle permits a wide range of selection with
the source clocks divided.
The timer is comprised of registers such as TCNTR, TCR, TSR, LOSR, ICR0, ICR1, TCMR0,
and TCMR1.
CAN Interface: The CAN interface is a block that complies with the requirements for the CAN
bus data link controller. It meets all the DLC standards functions classified into an OSI7 layer-
referenced model.
In order to comply with the standards given in the CAN bus, these functions are composed of the
bit configuration register (BCR) including REC and TEC and of registers and logics in various
control modes. As a CAN data link controller, this block controls the functional classification of
data reception and transmission.
remote request bit, new message control bit, time trigger enable bit, and timer count values,
etc.
Rev. 2.00, 09/04, page 409 of 720