HD64F7047F50 Renesas Electronics America, HD64F7047F50 Datasheet - Page 28

• Manufacturer Part Number: HD64F7047F50
• Description: IC SUPERH MCU FLASH 256K 100QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047F50

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Figure 8.9 Chain Transfer........................................................................................................... 126
Figure 8.10 DTC Operation Timing Example (Normal Mode) .................................................. 127
Section 9 Bus State Controller (BSC)
Figure 9.1 BSC Block Diagram.................................................................................................. 134
Figure 9.2 Address Format ......................................................................................................... 136
Figure 9.3 Basic Timing of External Space Access.................................................................... 141
Figure 9.4 Wait State Timing of External Space Access (Software Wait Only) ........................ 142
Figure 9.5 Wait State Timing of External Space Access (Two Software Wait States + WAIT
Signal Wait State)...................................................................................................... 143
Figure 9.6 CS Assert Period Extension Function ....................................................................... 144
Figure 9.7 Example of Idle Cycle Insertion at Same Space Consecutive Access....................... 145
Figure 9.8 Bus Mastership Release Procedure ........................................................................... 147
Figure 9.9 Example of 8-bit Data Bus Width ROM Connection................................................ 147
Figure 9.10 One Bus Cycle......................................................................................................... 148
Section 10 Multi-Function Timer Pulse Unit (MTU)
Figure 10.1 Block Diagram of MTU .......................................................................................... 152
Figure 10.2 Complementary PWM Mode Output Level Example ............................................. 190
Figure 10.3 Example of Counter Operation Setting Procedure .................................................. 194
Figure 10.4 Free-Running Counter Operation ............................................................................ 195
Figure 10.5 Periodic Counter Operation..................................................................................... 196
Figure 10.6 Example of Setting Procedure for Waveform Output by Compare Match.............. 196
Figure 10.7 Example of 0 Output/1 Output Operation ............................................................... 197
Figure 10.8 Example of Toggle Output Operation ..................................................................... 197
Figure 10.9 Example of Input Capture Operation Setting Procedure ......................................... 198
Figure 10.10 Example of Input Capture Operation .................................................................... 199
Figure 10.11 Example of Synchronous Operation Setting Procedure ........................................ 200
Figure 10.12 Example of Synchronous Operation...................................................................... 201
Figure 10.13 Compare Match Buffer Operation......................................................................... 202
Figure 10.14 Input Capture Buffer Operation............................................................................. 203
Figure 10.15 Example of Buffer Operation Setting Procedure................................................... 203
Figure 10.16 Example of Buffer Operation (1) .......................................................................... 204
Figure 10.17 Example of Buffer Operation (2) .......................................................................... 205
Figure 10.18 Cascaded Operation Setting Procedure ................................................................. 206
Figure 10.19 Example of Cascaded Operation ........................................................................... 207
Figure 10.20 Example of PWM Mode Setting Procedure .......................................................... 209
Figure 10.21 Example of PWM Mode Operation (1) ................................................................. 209
Figure 10.22 Example of PWM Mode Operation (2) ................................................................. 210
Figure 10.23 Example of PWM Mode Operation (3) ................................................................. 211
Figure 10.24 Example of Phase Counting Mode Setting Procedure........................................... 212
Figure 10.25 Example of Phase Counting Mode 1 Operation .................................................... 213
Figure 10.26 Example of Phase Counting Mode 2 Operation .................................................... 214
Figure 10.27 Example of Phase Counting Mode 3 Operation .................................................... 215
Rev. 2.00, 09/04, page xxvi of xl