HD64F7047F50 Renesas Electronics America, HD64F7047F50 Datasheet - Page 100

• Manufacturer Part Number: HD64F7047F50
• Description: IC SUPERH MCU FLASH 256K 100QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047F50

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

5.1.2
The exception processing sources are detected and the processing starts according to the timing
shown in table 5.2.
Table 5.2
When exception processing starts, the CPU operates as follows:
1. Exception processing triggered by reset:
2. Exception processing triggered by address errors, interrupts and instructions:
Rev. 2.00, 09/04, page 58 of 720
Exception
Reset
Address error
Interrupts
Instructions
The initial values of the program counter (PC) and stack pointer (SP) are fetched from the
exception processing vector table (PC and SP are respectively the H'00000000 and
H'00000004 addresses for power-on resets and the H'00000008 and H'0000000C addresses for
manual resets). See section 5.1.3, Exception Processing Vector Table, for more information.
H'00000000 is then written to the vector base register (VBR) , and H'F (B'1111) is written to
the interrupt mask bits (I3 to I0) of the status register (SR). The program begins running from
the PC address fetched from the exception processing vector table.
SR and PC are saved to the stack indicated by R15. For interrupt exception processing, the
interrupt priority level is written to the SR’s interrupt mask bits (I3 to I0). For address error
and instruction exception processing, the I3 to I0 bits are not affected. The start address is then
fetched from the exception processing vector table and the program begins running from that
address.
Exception Processing Operations
Timing for Exception Source Detection and Start of Exception Processing
Source
Power-on reset
Manual reset
Trap instruction
General illegal
instructions
Illegal slot
instructions
Timing of Source Detection and Start of Processing
Starts when the RES pin changes from low to high or when
WDT overflows.
Starts when the MRES pin changes from low to high.
Detected when instruction is decoded and starts when the
execution of the previous instruction is completed.
Starts from the execution of a TRAPA instruction.
Starts from the decoding of undefined code anytime except
after a delayed branch instruction (delay slot).
Starts from the decoding of undefined code placed in a delayed
branch instruction (delay slot) or of instructions that rewrite the
PC.