HD64F7047F50 Renesas Electronics America, HD64F7047F50 Datasheet - Page 424

• Manufacturer Part Number: HD64F7047F50
• Description: IC SUPERH MCU FLASH 256K 100QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047F50

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

13.3
The A/D converter has the following registers. For details on register addresses, refer to appendix
A, Internal I/O Register.
• A/D data register 0 (H/L) (ADDR0)
• A/D data register 1 (H/L) (ADDR1)
• A/D data register 2 (H/L) (ADDR2)
• A/D data register 3 (H/L) (ADDR3)
• A/D data register 4 (H/L) (ADDR4)
• A/D data register 5 (H/L) (ADDR5)
• A/D data register 6 (H/L) (ADDR6)
• A/D data register 7 (H/L) (ADDR7)
• A/D data register 8 (H/L) (ADDR8)
• A/D data register 9 (H/L) (ADDR9)
• A/D data register 10 (H/L) (ADDR10)
• A/D data register 11 (H/L) (ADDR11)
• A/D data register 12 (H/L) (ADDR12)
• A/D data register 13 (H/L) (ADDR13)
• A/D data register 14 (H/L) (ADDR14)
• A/D data register 15 (H/L) (ADDR15)
• A/D control/status register_0 (ADCSR_0)
• A/D control/status register_1 (ADCSR_1)
• A/D control register_0 (ADCR_0)
• A/D control register_1 (ADCR_1)
• A/D trigger select register (ADTSR)
13.3.1
ADDRs are 16-bit read-only registers. The conversion result for each analog input channel is
stored in ADDR with the corresponding number. (For example, the conversion result of AN4 is
stored in ADDR4.)
The converted 10-bit data is stored in bits 6 to 15. The lower 6 bits are always read as 0.
The data bus between the CPU and the A/D converter is 8 bits wide. The upper byte can be read
directly from the CPU, however the lower byte should be read via a temporary register. The
temporary register contents are transferred from the ADDR when the upper byte data is read.
When reading the ADDR, read the upper byte before the lower byte, or read in word unit. The
initial value of ADDR is H'0000.
Rev. 2.00, 09/04, page 382 of 720
Register Description
A/D Data Registers 0 to 15 (ADDR0 to ADDR15)