HD64F7047F50 Renesas Electronics America, HD64F7047F50 Datasheet - Page 202

• Manufacturer Part Number: HD64F7047F50
• Description: IC SUPERH MCU FLASH 256K 100QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047F50

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

10.3.2
The TMDR registers are 8-bit readable/writable registers that are used to set the operating mode of
each channel. The MTU has five TMDR registers, one for each channel. TMDR register settings
should be changed only when TCNT operation is stopped.
Rev. 2.00, 09/04, page 160 of 720
Bit
7, 6
5
4
3
2
1
0
Bit Name

MD3
MD2
MD1
MD0
BFB
BFA
Timer Mode Register (TMDR)
Initial
value
All 1
0
0
0
0
0
0
R/W

R/W
R/W
R/W
R/W
R/W
R/W
Description
Reserved
These bits are always read as 1, and should only be
written with 1.
Buffer Operation B
Specifies whether TGRB is to operate in the normal way,
or TGRB and TGRD are to be used together for buffer
operation. When TGRD is used as a buffer register, TGRD
input capture/output compare is not generated.
In channels 1 and 2, which have no TGRD, bit 5 is
reserved. It is always read as 0, and should only be written
with 0.
0: TGRB and TGRD operate normally
1: TGRB and TGRD used together for buffer operation
Buffer Operation A
Specifies whether TGRA is to operate in the normal way,
or TGRA and TGRC are to be used together for buffer
operation. When TGRC is used as a buffer register, TGRC
input capture/output compare is not generated.
In channels 1 and 2, which have no TGRC, bit 4 is
reserved. It is always read as 0, and should only be written
with 0.
0: TGRA and TGRC operate normally
1: TGRA and TGRC used together for buffer operation
Modes 0 to 3
These bits are used to set the timer operating mode.
See table 10.9 for details.