HD64F7047F50 Renesas Electronics America, HD64F7047F50 Datasheet - Page 181

• Manufacturer Part Number: HD64F7047F50
• Description: IC SUPERH MCU FLASH 256K 100QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047F50

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

9.5.2
BCR2 is a 16-bit readable/writable register that specifies the number of idle cycles and CS0 signal
assert extension of each CS0 space.
Bit
15 to 10 
9
8
7 to 5
4
3 to 1
0
Bus Control Register 2 (BCR2)
Bit Name
IW01
IW00

CW0

SW0
Initial
Value
All 1
1
1
All 1
1
All 1
1
R/W
R
R/W
R/W
R
R/W
R
R/W
Description
Reserved
These bits are always read as 1 and should always
be written with 1.
Idle Specification between Cycles
These bits insert idle cycles when a read access is
followed immediately by a write access.
00: No CS0 space idle cycle
01: One CS0 space idle cycle
10: Two CS0 space idle cycles
11: Three CS0 space idle cycles
Reserved
These bits are always read as 1 and should always
be written with 1.
Idle Specification for Continuous Access
The continuous access idle specification makes
insertions to clearly delineate the bus intervals by
once negating the CS0 signal when performing
consecutive accesses to the same CS space.
0: No CS0 space continuous access idle cycles
1: One CS0 space continuous access idle cycle
When a write immediately follows a read, the number
of idle cycles inserted is the larger of the two values
specified by IWO1 and IWO0.
Reserved
These bits are always read as 1 and should always
be written with 1.
CS Assert Extension Specification
The CS assert cycle extension specification is for
making insertions to prevent extension of the RD
signal or WRL signal assert period beyond the length
of the CS0 signal assert period.
0: No CS0 space CS assert extension
1: CS0 space CS assert extension (one cycle is
inserted before and after each bus cycle)
Rev. 2.00, 09/04, page 139 of 720