HD64F7047F50 Renesas Electronics America, HD64F7047F50 Datasheet - Page 570

• Manufacturer Part Number: HD64F7047F50
• Description: IC SUPERH MCU FLASH 256K 100QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047F50

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Notes: 1. F-ZTAT only. Setting prohibited for the mask version.
Rev. 2.00, 09/04, page 528 of 720
Register
PACRL3
PACRL2
PACRL2
PACRL3
PACRL2
PACRL2
PACRL3
PACRL2
PACRL2
PACRL3
PACRL2
PACRL2
PACRL3
PACRL2
PACRL2
2. The initial value is 1 in the E10A debugging mode which is specified by a low level on
3. The initial value is 1 in the on-chip ROM disabled 8-bit external-expansion mode.
Bit
4
9
8
3
7
6
2
5
4
1
3
2
0
1
0
DBGMD.
Bit Name
PA4MD2
PA4MD1
PA4MD0
PA3MD2
PA3MD1
PA3MD0
PA2MD2
PA2MD1
PA2MD0
PA1MD2
PA1MD1
PA1MD0
PA0MD2
PA0MD1
PA0MD0
Initial
Value
0*
0
0
0*
0
0
0*
0
0
0*
0
0
0*
0
0
3
3
3
3
3
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
PA4 Mode
Select the function of the PA4/A4/POE5/TXD3 pin.
000: PA4 I/O (port)
001: Setting prohibited
010: Setting prohibited
011: Setting prohibited
PA3 Mode
Select the function of the PA3/A3/POE4/RXD3 pin.
000: PA3 I/O (port)
001: Setting prohibited
010: Setting prohibited
011: Setting prohibited
PA2 Mode
Select the function of the PA2/IRQ0/A2/PCIO/SCK2 pin.
000: PA2 I/O (port)
001: Setting prohibited
010: Setting prohibited
011: IRQ0 input (INTC)
PA1 Mode
Select the function of the PA1/A1/POE1/TXD2 pin.
000: PA1 I/O (port)
001: Setting prohibited
010: Setting prohibited
011: Setting prohibited
PA0 Mode
Select the function of the PA0/A0/POE0/RXD2 pin.
000: PA0 I/O (port)
001: Setting prohibited
010: Setting prohibited
011: Setting prohibited
100: A4 output (BSC)
101: POE5 input (port)
110: TXD3 output (SCI)
111: Setting prohibited
100: A3 output (BSC)
101: POE4 input (port)
110: RXD3 input (SCI)
111: Setting prohibited
100: A2 output (BSC)
101: PCIO I/O (MMT)
110: SCK2 I/O (SCI)
111: Setting prohibited
100: A1 output (BSC)
101: POE1 input (port)
110: TXD2 output (SCI)
111: Setting prohibited
100: A0 output (BSC)
101: POE0 input (port)
110: RXD2 input (SCI)
111: Setting prohibited