HD64F7047F50 Renesas Electronics America, HD64F7047F50 Datasheet - Page 415

• Manufacturer Part Number: HD64F7047F50
• Description: IC SUPERH MCU FLASH 256K 100QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047F50

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the ORER,
FER, PER, and RDRF bits to 0 before resuming reception. Figure 12.19 shows a sample
flowchart for serial data reception.
[3]
No
No
Read receive data in RDR, and
clear RDRF flag in SSR to 0
Clear ORER flag in SSR to 0
Read ORER flag in SSR
Read RDRF flag in SSR
Clear RE bit in SCR to 0
Overrun error processing
All data received?
Error processing
Start reception
Initialization
ORER = 1
RDRF = 1
Figure 12.19 Sample Serial Reception Flowchart
<End>
<End>
Yes
Yes
No
(Continued below)
Error processing
Yes
[2]
[1]
[3]
[4]
[5]
[1] SCI initialization:
[2] [3] Receive error processing:
[4] SCI status check and receive data
[5] Serial reception continuation
Set the RxD pin using the PFC.
If a receive error occurs, read the
ORER flag in SSR, and after
performing the appropriate error
processing, clear the ORER flag to 0.
Transfer cannot be resumed if the
ORER flag is set to 1.
read:
Read SSR and check that the RDRF
flag is set to 1, then read the receive
data in RDR and clear the RDRF flag
to 0.
Transition of the RDRF flag from 0 to 1
can also be identified by an RXI
interrupt.
procedure:
To continue serial reception, before
the MSB (bit 7) of the current frame is
received, reading the RDRF flag,
reading RDR, and clearing the RDRF
flag to 0 should be finished. The
RDRF flag is cleared automatically
when the DTC is activated by a
receive data full interrupt (RXI) request
and the RDR value is read.
Rev. 2.00, 09/04, page 373 of 720